101 lines
2.9 KiB
ArmAsm
101 lines
2.9 KiB
ArmAsm
/*
|
|
* Copyright (c) 2019, Arm Limited and Contributors. All rights reserved.
|
|
*
|
|
* SPDX-License-Identifier: BSD-3-Clause
|
|
*/
|
|
|
|
#include <arch.h>
|
|
#include <asm_macros.S>
|
|
#include <platform_def.h>
|
|
|
|
.globl plat_secondary_cold_boot_setup
|
|
.globl plat_get_my_entrypoint
|
|
.globl plat_is_my_cpu_primary
|
|
.globl plat_arm_calc_core_pos
|
|
|
|
/* --------------------------------------------------------------------
|
|
* void plat_secondary_cold_boot_setup (void);
|
|
*
|
|
* For AArch32, cold-booting secondary CPUs is not yet
|
|
* implemented and they panic.
|
|
* --------------------------------------------------------------------
|
|
*/
|
|
func plat_secondary_cold_boot_setup
|
|
cb_panic:
|
|
b cb_panic
|
|
endfunc plat_secondary_cold_boot_setup
|
|
|
|
/* ---------------------------------------------------------------------
|
|
* unsigned long plat_get_my_entrypoint (void);
|
|
*
|
|
* Main job of this routine is to distinguish between a cold and warm
|
|
* boot. On Corstone700, this information can be queried from the power
|
|
* controller. The Power Control SYS Status Register (PSYSR) indicates
|
|
* the wake-up reason for the CPU.
|
|
*
|
|
* For a cold boot, return 0.
|
|
* For a warm boot, Not yet supported.
|
|
*
|
|
* TODO: PSYSR is a common register and should be
|
|
* accessed using locks. Since it is not possible
|
|
* to use locks immediately after a cold reset
|
|
* we are relying on the fact that after a cold
|
|
* reset all cpus will read the same WK field
|
|
* ---------------------------------------------------------------------
|
|
*/
|
|
func plat_get_my_entrypoint
|
|
/* TODO support warm boot */
|
|
/* Cold reset */
|
|
mov r0, #0
|
|
bx lr
|
|
endfunc plat_get_my_entrypoint
|
|
|
|
/* -----------------------------------------------------
|
|
* unsigned int plat_is_my_cpu_primary (void);
|
|
*
|
|
* Find out whether the current CPU is the primary
|
|
* CPU.
|
|
* -----------------------------------------------------
|
|
*/
|
|
func plat_is_my_cpu_primary
|
|
ldcopr r0, MPIDR
|
|
ldr r1, =MPIDR_AFFINITY_MASK
|
|
and r0, r1
|
|
cmp r0, #0
|
|
moveq r0, #1
|
|
movne r0, #0
|
|
bx lr
|
|
endfunc plat_is_my_cpu_primary
|
|
|
|
/* ---------------------------------------------------------------------
|
|
* unsigned int plat_arm_calc_core_pos(u_register_t mpidr)
|
|
*
|
|
* Function to calculate the core position on Corstone700.
|
|
*
|
|
* (ClusterId * MAX_CPUS_PER_CLUSTER * MAX_PE_PER_CPU) +
|
|
* (CPUId * MAX_PE_PER_CPU) +
|
|
* ThreadId
|
|
*
|
|
* which can be simplified as:
|
|
*
|
|
* ((ClusterId * MAX_CPUS_PER_CLUSTER + CPUId) * MAX_PE_PER_CPU)
|
|
* + ThreadId
|
|
* ---------------------------------------------------------------------
|
|
*/
|
|
func plat_arm_calc_core_pos
|
|
mov r3, r0
|
|
|
|
/* Extract individual affinity fields from MPIDR */
|
|
ubfx r0, r3, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
|
|
ubfx r1, r3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
|
|
ubfx r2, r3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
|
|
|
|
/* Compute linear position */
|
|
mov r3, #CORSTONE700_MAX_CPUS_PER_CLUSTER
|
|
mla r1, r2, r3, r1
|
|
mov r3, #CORSTONE700_MAX_PE_PER_CPU
|
|
mla r0, r1, r3, r0
|
|
|
|
bx lr
|
|
endfunc plat_arm_calc_core_pos
|