84 lines
1.9 KiB
C
84 lines
1.9 KiB
C
/*
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* Copyright 2021 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#ifndef SOC_DEFAULT_HELPER_MACROS_H
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#define SOC_DEFAULT_HELPER_MACROS_H
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#ifdef NXP_OCRAM_TZPC_ADDR
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/* 0x1: means 4 KB
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* 0x2: means 8 KB
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*/
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#define TZPC_BLOCK_SIZE 0x1000
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#endif
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/* DDR controller offsets and defines */
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#ifdef NXP_DDR_ADDR
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#define DDR_CFG_2_OFFSET 0x114
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#define CFG_2_FORCE_REFRESH 0x80000000
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#endif /* NXP_DDR_ADDR */
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/* Reset block register offsets */
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#ifdef NXP_RESET_ADDR
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/* Register Offset */
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#define RST_RSTCR_OFFSET 0x0
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#define RST_RSTRQMR1_OFFSET 0x10
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#define RST_RSTRQSR1_OFFSET 0x18
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#define BRR_OFFSET 0x60
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/* helper macros */
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#define RSTRQSR1_SWRR 0x800
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#define RSTRQMR_RPTOE_MASK (1 << 19)
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#endif /* NXP_RESET_ADDR */
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/* Secure-Register-File register offsets and bit masks */
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#ifdef NXP_RST_ADDR
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/* Register Offset */
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#define CORE_HOLD_OFFSET 0x140
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#define RSTCNTL_OFFSET 0x180
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/* Helper macros */
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#define SW_RST_REQ_INIT 0x1
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#endif
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#ifdef NXP_RCPM_ADDR
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/* RCPM Register Offsets */
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#define RCPM_PCPH20SETR_OFFSET 0x0D4
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#define RCPM_PCPH20CLRR_OFFSET 0x0D8
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#define RCPM_POWMGTCSR_OFFSET 0x130
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#define RCPM_IPPDEXPCR0_OFFSET 0x140
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#define RCPM_POWMGTCSR_LPM20_REQ 0x00100000
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#define RCPM2_IPSTPCR0_OFFSET 0x8
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#define RCPM2_IPSTPCR1_OFFSET 0xC
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#define RCPM2_IPSTPCR2_OFFSET 0x10
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#define RCPM2_IPSTPCR3_OFFSET 0x14
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#define RCPM2_IPSTPCR4_OFFSET 0x28
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#define RCPM2_IPSTPACKR0_OFFSET 0x18
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#define RCPM2_IPSTPACKR1_OFFSET 0x1C
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#define RCPM2_IPSTPACKR2_OFFSET 0x20
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#define RCPM2_IPSTPACKR3_OFFSET 0x24
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#define RCPM2_IPSTPACKR4_OFFSET 0x2C
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#define RCPM2_POWMGTDCR_OFFSET 0x0
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/* bitfield masks */
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#define POWMGTDCR_OVRD_EN 0x80000000
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#endif /* NXP_RCPM_ADDR */
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#define DCFG_SBEESR2_ADDR 0x20140534
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#define DCFG_MBEESR2_ADDR 0x20140544
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/* SBEESR and MBEESR bit mask */
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#define OCRAM_EESR_MASK 0x00000060
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#endif /* SOC_DEFAULT_HELPER_MACROS_H */
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