Antonio Nino Diaz d3d6c6e3e9 Assert correct granularity when mapping a PA ... Each translation table level entry can only map a given virtual address onto physical addresses of the same granularity. For example, with the current configuration, a level 2 entry maps blocks of 2 MB, so the physical address must be aligned to 2 MB. If the address is not aligned, the MMU will just ignore the lower bits. This patch adds an assertion to make sure that physical addresses are always aligned to the correct boundary. Change-Id: I0ab43df71829d45cdbe323301b3053e08ca99c2c Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>		2016-12-13 15:35:15 +00:00
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bl1	FWU: Add Generic Firmware Update framework support in BL1	2015-12-09 17:41:18 +00:00
bl31	Introduce PSCI Library Interface	2016-07-19 10:19:01 +01:00
bl32	AArch32: Support in SP_MIN to receive arguments from BL2	2016-09-21 16:28:46 +01:00
common	Merge pull request #774 from jeenu-arm/no-return-macro	2016-12-12 14:29:01 +00:00
drivers	emmc/sd: for C99 compliance, changed the unsigned char/short bitfield to unsigned int bitfields	2016-12-01 22:43:21 +08:00
lib	Assert correct granularity when mapping a PA	2016-12-13 15:35:15 +00:00
plat	Allow ARM Standard platforms to dynamically define PSCI capability	2016-12-07 12:45:55 +00:00
services	PSCI: Do psci_setup() as part of std_svc_setup()	2016-09-22 17:07:20 +01:00