255 lines
7.5 KiB
ArmAsm
255 lines
7.5 KiB
ArmAsm
/*
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* Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <bl_common.h>
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#include <cortex_a53.h>
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#include <cortex_a72.h>
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#include <plat_private.h>
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#include <platform_def.h>
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.globl cpuson_entry_point
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.globl cpuson_flags
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.globl platform_cpu_warmboot
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.globl plat_secondary_cold_boot_setup
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.globl plat_report_exception
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.globl platform_is_primary_cpu
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.globl plat_crash_console_init
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.globl plat_crash_console_putc
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.globl plat_my_core_pos
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.globl plat_reset_handler
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#define RK_REVISION(rev) RK_PLAT_CFG##rev
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#define RK_HANDLER(rev) plat_reset_handler_juno_r##rev
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#define JUMP_TO_HANDLER_IF_RK_R(revision) \
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jump_to_handler RK_REVISION(revision), RK_HANDLER(revision)
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/*
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* Helper macro to jump to the given handler if the board revision
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* matches.
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* Expects the Juno board revision in x0.
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*
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*/
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.macro jump_to_handler _revision, _handler
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cmp x0, #\_revision
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b.eq \_handler
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.endm
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/*
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* Helper macro that reads the part number of the current CPU and jumps
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* to the given label if it matches the CPU MIDR provided.
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*/
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.macro jump_if_cpu_midr _cpu_midr, _label
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mrs x0, midr_el1
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ubfx x0, x0, MIDR_PN_SHIFT, #12
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cmp w0, #((\_cpu_midr >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
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b.eq \_label
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.endm
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/*
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* Platform reset handler for rockchip.
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* only A53 cores
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*/
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func RK_HANDLER(0)
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ret
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endfunc RK_HANDLER(0)
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/*
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* Platform reset handler for rockchip.
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* - Cortex-A53 processor cluster;
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* - Cortex-A72 processor cluster.
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*
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* This handler does the following:
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* - Set the L2 Data RAM latency to 2 (i.e. 3 cycles) for Cortex-A72
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* - Set the L2 Tag RAM latency to 1 (i.e. 2 cycles) for Cortex-A72
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*/
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func RK_HANDLER(1)
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/*
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* Nothing to do on Cortex-A53.
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*
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*/
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jump_if_cpu_midr CORTEX_A72_MIDR, A72
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ret
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A72:
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/* Cortex-A72 specific settings */
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mov x0, #((2 << L2CTLR_DATA_RAM_LATENCY_SHIFT) | \
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(0x1 << 5))
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msr L2CTLR_EL1, x0
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isb
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ret
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endfunc RK_HANDLER(1)
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/*
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* void plat_reset_handler(void);
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*
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* Determine the SOC type and call the appropriate reset
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* handler.
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*
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*/
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func plat_reset_handler
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mov x0, RK_PLAT_AARCH_CFG
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JUMP_TO_HANDLER_IF_RK_R(0)
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JUMP_TO_HANDLER_IF_RK_R(1)
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/* SOC type is not supported */
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not_supported:
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b not_supported
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endfunc plat_reset_handler
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func plat_my_core_pos
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mrs x0, mpidr_el1
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and x1, x0, #MPIDR_CPU_MASK
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and x0, x0, #MPIDR_CLUSTER_MASK
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add x0, x1, x0, LSR #6
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ret
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endfunc plat_my_core_pos
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/* --------------------------------------------------------------------
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* void plat_secondary_cold_boot_setup (void);
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*
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* This function performs any platform specific actions
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* needed for a secondary cpu after a cold reset e.g
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* mark the cpu's presence, mechanism to place it in a
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* holding pen etc.
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* --------------------------------------------------------------------
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*/
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func plat_secondary_cold_boot_setup
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/* rk3368 does not do cold boot for secondary CPU */
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cb_panic:
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b cb_panic
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endfunc plat_secondary_cold_boot_setup
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func platform_is_primary_cpu
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and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
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cmp x0, #PLAT_RK_PRIMARY_CPU
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cset x0, eq
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ret
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endfunc platform_is_primary_cpu
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/* --------------------------------------------------------------------
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* int plat_crash_console_init(void)
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* Function to initialize the crash console
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* without a C Runtime to print crash report.
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* Clobber list : x0, x1, x2
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* --------------------------------------------------------------------
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*/
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func plat_crash_console_init
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mov_imm x0, PLAT_RK_UART_BASE
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mov_imm x1, PLAT_RK_UART_CLOCK
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mov_imm x2, PLAT_RK_UART_BAUDRATE
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b console_core_init
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endfunc plat_crash_console_init
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/* --------------------------------------------------------------------
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* int plat_crash_console_putc(void)
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* Function to print a character on the crash
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* console without a C Runtime.
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* Clobber list : x1, x2
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* --------------------------------------------------------------------
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*/
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func plat_crash_console_putc
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mov_imm x1, PLAT_RK_UART_BASE
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b console_core_putc
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endfunc plat_crash_console_putc
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/* --------------------------------------------------------------------
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* void platform_cpu_warmboot (void);
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* cpus online or resume enterpoint
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* --------------------------------------------------------------------
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*/
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.align 16
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func platform_cpu_warmboot
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mrs x0, MPIDR_EL1
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and x1, x0, #MPIDR_CPU_MASK
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and x0, x0, #MPIDR_CLUSTER_MASK
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/* --------------------------------------------------------------------
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* big cluster id is 1
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* big cores id is from 0-3, little cores id 4-7
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* --------------------------------------------------------------------
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*/
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add x0, x1, x0, lsr #6
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/* --------------------------------------------------------------------
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* get per cpuup flag
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* --------------------------------------------------------------------
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*/
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adr x4, cpuson_flags
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add x4, x4, x0, lsl #2
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ldr w1, [x4]
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/* --------------------------------------------------------------------
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* check cpuon reason
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* --------------------------------------------------------------------
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*/
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ldr w3, =PMU_CPU_AUTO_PWRDN
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cmp w1, w3
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b.eq boot_entry
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ldr w3, =PMU_CPU_HOTPLUG
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cmp w1, w3
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b.eq boot_entry
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/* --------------------------------------------------------------------
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* If the boot core cpuson_flags or cpuson_entry_point is not
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* expection. force the core into wfe.
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* --------------------------------------------------------------------
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*/
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wfe_loop:
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wfe
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b wfe_loop
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boot_entry:
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mov w1, #0
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str w1, [x4]
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/* --------------------------------------------------------------------
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* get per cpuup boot addr
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* --------------------------------------------------------------------
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*/
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adr x5, cpuson_entry_point
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ldr x2, [x5, x0, lsl #3]
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br x2
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endfunc platform_cpu_warmboot
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/* --------------------------------------------------------------------
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* Per-CPU Secure entry point - resume or power up
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* --------------------------------------------------------------------
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*/
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.section tzfw_coherent_mem, "a"
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.align 3
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cpuson_entry_point:
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.rept PLATFORM_CORE_COUNT
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.quad 0
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.endr
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cpuson_flags:
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.rept PLATFORM_CORE_COUNT
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.word 0
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.endr
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