57 lines
1.7 KiB
C
57 lines
1.7 KiB
C
/*
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* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef MEMCTRL_V1_H
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#define MEMCTRL_V1_H
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#include <mmio.h>
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#include <tegra_def.h>
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/* SMMU registers */
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#define MC_SMMU_CONFIG_0 0x10U
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#define MC_SMMU_CONFIG_0_SMMU_ENABLE_DISABLE 0U
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#define MC_SMMU_CONFIG_0_SMMU_ENABLE_ENABLE 1U
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#define MC_SMMU_TLB_CONFIG_0 0x14U
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#define MC_SMMU_TLB_CONFIG_0_RESET_VAL 0x20000010U
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#define MC_SMMU_PTC_CONFIG_0 0x18U
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#define MC_SMMU_PTC_CONFIG_0_RESET_VAL 0x2000003fU
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#define MC_SMMU_TLB_FLUSH_0 0x30U
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#define TLB_FLUSH_VA_MATCH_ALL 0U
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#define TLB_FLUSH_ASID_MATCH_DISABLE 0U
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#define TLB_FLUSH_ASID_MATCH_SHIFT 31U
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#define MC_SMMU_TLB_FLUSH_ALL \
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(TLB_FLUSH_VA_MATCH_ALL | \
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(TLB_FLUSH_ASID_MATCH_DISABLE << TLB_FLUSH_ASID_MATCH_SHIFT))
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#define MC_SMMU_PTC_FLUSH_0 0x34U
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#define MC_SMMU_PTC_FLUSH_ALL 0U
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#define MC_SMMU_ASID_SECURITY_0 0x38U
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#define MC_SMMU_ASID_SECURITY 0U
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#define MC_SMMU_TRANSLATION_ENABLE_0_0 0x228U
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#define MC_SMMU_TRANSLATION_ENABLE_1_0 0x22cU
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#define MC_SMMU_TRANSLATION_ENABLE_2_0 0x230U
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#define MC_SMMU_TRANSLATION_ENABLE_3_0 0x234U
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#define MC_SMMU_TRANSLATION_ENABLE_4_0 0xb98U
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#define MC_SMMU_TRANSLATION_ENABLE (~0)
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/* MC IRAM aperture registers */
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#define MC_IRAM_BASE_LO 0x65CU
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#define MC_IRAM_TOP_LO 0x660U
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#define MC_IRAM_BASE_TOP_HI 0x980U
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#define MC_IRAM_REG_CTRL 0x964U
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#define MC_DISABLE_IRAM_CFG_WRITES 1U
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static inline uint32_t tegra_mc_read_32(uint32_t off)
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{
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return mmio_read_32(TEGRA_MC_BASE + off);
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}
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static inline void tegra_mc_write_32(uint32_t off, uint32_t val)
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{
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mmio_write_32(TEGRA_MC_BASE + off, val);
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}
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#endif /* MEMCTRL_V1_H */
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