79 lines
1.9 KiB
C
79 lines
1.9 KiB
C
/*
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <assert.h>
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#include <console.h>
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#include <debug.h>
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#include <generic_delay_timer.h>
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#include <gicv2.h>
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#include <platform.h>
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#include <platform_def.h>
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#include <sunxi_def.h>
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#include <sunxi_mmap.h>
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#include <uart_16550.h>
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#include "sunxi_private.h"
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static entry_point_info_t bl33_image_ep_info;
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static console_16550_t console;
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static const gicv2_driver_data_t sunxi_gic_data = {
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.gicd_base = SUNXI_GICD_BASE,
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.gicc_base = SUNXI_GICC_BASE,
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};
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void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
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u_register_t arg2, u_register_t arg3)
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{
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/* Initialize the debug console as soon as possible */
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console_16550_register(SUNXI_UART0_BASE, SUNXI_UART0_CLK_IN_HZ,
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SUNXI_UART0_BAUDRATE, &console);
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/* Populate entry point information for BL33 */
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SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0);
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/*
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* Tell BL31 where the non-trusted software image
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* is located and the entry state information
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*/
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bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
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bl33_image_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX,
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DISABLE_ALL_EXCEPTIONS);
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SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
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/* Turn off all secondary CPUs */
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sunxi_disable_secondary_cpus(plat_my_core_pos());
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}
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void bl31_plat_arch_setup(void)
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{
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sunxi_configure_mmu_el3(0);
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}
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void bl31_platform_setup(void)
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{
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generic_delay_timer_init();
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/* Configure the interrupt controller */
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gicv2_driver_init(&sunxi_gic_data);
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gicv2_distif_init();
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gicv2_pcpu_distif_init();
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gicv2_cpuif_enable();
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sunxi_security_setup();
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INFO("BL31: Platform setup done\n");
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}
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entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
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{
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assert(sec_state_is_valid(type) != 0);
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assert(type == NON_SECURE);
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return &bl33_image_ep_info;
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}
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