243 lines
7.3 KiB
C
243 lines
7.3 KiB
C
/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef SGM_BASE_PLATFORM_DEF_H
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#define SGM_BASE_PLATFORM_DEF_H
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#include <drivers/arm/tzc400.h>
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#include <drivers/arm/tzc_common.h>
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#include <plat/arm/board/common/board_css_def.h>
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#include <plat/arm/board/common/v2m_def.h>
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#include <plat/arm/common/arm_def.h>
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#include <plat/arm/css/common/css_def.h>
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#include <plat/arm/soc/common/soc_css_def.h>
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#include <plat/common/common_def.h>
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/* CPU topology */
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#define PLAT_ARM_CLUSTER_COUNT 1
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#define PLAT_ARM_CLUSTER_CORE_COUNT 8
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#define PLATFORM_CORE_COUNT PLAT_ARM_CLUSTER_CORE_COUNT
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#define PLAT_MAX_PWR_LVL ARM_PWR_LVL2
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#define PLAT_NUM_PWR_DOMAINS (ARM_SYSTEM_COUNT + \
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PLAT_ARM_CLUSTER_COUNT + \
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PLATFORM_CORE_COUNT)
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/*
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* Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
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* terminology. On a GICv2 system or mode, the lists will be merged and treated
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* as Group 0 interrupts.
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*/
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#define PLAT_ARM_G1S_IRQ_PROPS(grp) \
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CSS_G1S_IRQ_PROPS(grp), \
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ARM_G1S_IRQ_PROPS(grp)
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#define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp)
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/* GIC related constants */
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#define PLAT_ARM_GICD_BASE 0x30000000
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#define PLAT_ARM_GICR_BASE 0x300C0000
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#define PLAT_ARM_GICC_BASE 0x2c000000
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#define CSS_GIC_SIZE 0x00200000
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#define CSS_MAP_GIC_DEVICE MAP_REGION_FLAT( \
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PLAT_ARM_GICD_BASE, \
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CSS_GIC_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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/* Platform ID address */
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#define SSC_VERSION (SSC_REG_BASE + SSC_VERSION_OFFSET)
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#ifndef __ASSEMBLER__
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/* SSC_VERSION related accessors */
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/* Returns the part number of the platform */
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#define GET_PLAT_PART_NUM \
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GET_SSC_VERSION_PART_NUM(mmio_read_32(SSC_VERSION))
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/* Returns the configuration number of the platform */
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#define GET_PLAT_CONFIG_NUM \
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GET_SSC_VERSION_CONFIG(mmio_read_32(SSC_VERSION))
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#endif /* __ASSEMBLER__ */
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/*************************************************************************
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* Definitions common to all SGM CSS based platforms
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*************************************************************************/
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/* TZC-400 related constants */
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#define PLAT_ARM_TZC_BASE 0x2a500000
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#define TZC_NSAID_ALL_AP 0 /* Note: Same as default NSAID!! */
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#define TZC_NSAID_HDLCD0 2
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#define TZC_NSAID_HDLCD1 3
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#define TZC_NSAID_GPU 9
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#define TZC_NSAID_VIDEO 10
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#define TZC_NSAID_DISP0 11
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#define TZC_NSAID_DISP1 12
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/*************************************************************************
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* Required platform porting definitions common to all SGM CSS based
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* platforms
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*************************************************************************/
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#define PLAT_ARM_TRUSTED_SRAM_SIZE 0x00040000 /* 256 KB */
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/* MHU related constants */
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#define PLAT_CSS_MHU_BASE 0x2b1f0000
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#define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE
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#define PLAT_ARM_TRUSTED_ROM_BASE 0x00000000
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#define PLAT_ARM_TRUSTED_ROM_SIZE 0x00080000
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#define PLAT_ARM_CCI_BASE 0x2a000000
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/* Cluster to CCI slave mapping */
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#define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 6
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#define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 5
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/* System timer related constants */
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#define PLAT_ARM_NSTIMER_FRAME_ID 0
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/* TZC related constants */
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#define PLAT_ARM_TZC_NS_DEV_ACCESS ( \
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TZC_REGION_ACCESS_RDWR(TZC_NSAID_ALL_AP) | \
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TZC_REGION_ACCESS_RDWR(TZC_NSAID_HDLCD0) | \
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TZC_REGION_ACCESS_RDWR(TZC_NSAID_HDLCD1) | \
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TZC_REGION_ACCESS_RDWR(TZC_NSAID_GPU) | \
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TZC_REGION_ACCESS_RDWR(TZC_NSAID_VIDEO) | \
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TZC_REGION_ACCESS_RDWR(TZC_NSAID_DISP0) | \
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TZC_REGION_ACCESS_RDWR(TZC_NSAID_DISP1))
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/* Display Processor register definitions to setup the NSAIDs */
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#define MALI_DP_BASE 0x2cc00000
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#define DP_NPROT_NSAID_OFFSET 0x1000c
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#define W_NPROT_NSAID_SHIFT 24
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#define LS_NPORT_NSAID_SHIFT 12
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/*
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* Base address of the first memory region used for communication between AP
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* and SCP. Used by the BootOverMHU and SCPI protocols.
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*/
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#if !CSS_USE_SCMI_SDS_DRIVER
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/*
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* Note that this is located at the same address as SCP_BOOT_CFG_ADDR, which
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* means the SCP/AP configuration data gets overwritten when the AP initiates
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* communication with the SCP. The configuration data is expected to be a
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* 32-bit word on all CSS platforms. Part of this configuration is
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* which CPU is the primary, according to the shift and mask definitions below.
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*/
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#define PLAT_CSS_SCP_COM_SHARED_MEM_BASE (ARM_TRUSTED_SRAM_BASE + 0x80)
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#define PLAT_CSS_PRIMARY_CPU_SHIFT 8
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#define PLAT_CSS_PRIMARY_CPU_BIT_WIDTH 4
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#endif
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/*
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* PLAT_CSS_MAX_SCP_BL2_SIZE is calculated using the current
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* SCP_BL2 size plus a little space for growth.
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*/
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#define PLAT_CSS_MAX_SCP_BL2_SIZE 0x15000
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/*
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* PLAT_CSS_MAX_SCP_BL2U_SIZE is calculated using the current
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* SCP_BL2U size plus a little space for growth.
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*/
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#define PLAT_CSS_MAX_SCP_BL2U_SIZE 0x15000
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/*
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* Most platform porting definitions provided by included headers
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*/
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/*
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* PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the
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* plat_arm_mmap array defined for each BL stage.
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*/
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#if defined(IMAGE_BL31)
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# define PLAT_ARM_MMAP_ENTRIES 8
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# define MAX_XLAT_TABLES 5
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#elif defined(IMAGE_BL32)
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# define PLAT_ARM_MMAP_ENTRIES 8
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# define MAX_XLAT_TABLES 5
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#elif !USE_ROMLIB
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# define PLAT_ARM_MMAP_ENTRIES 11
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# define MAX_XLAT_TABLES 5
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#else
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# define PLAT_ARM_MMAP_ENTRIES 12
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# define MAX_XLAT_TABLES 6
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#endif
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/*
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* PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size
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* plus a little space for growth.
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*/
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#define PLAT_ARM_MAX_BL1_RW_SIZE 0xB000
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/*
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* PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page
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*/
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#if USE_ROMLIB
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#define PLAT_ARM_MAX_ROMLIB_RW_SIZE 0x1000
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#define PLAT_ARM_MAX_ROMLIB_RO_SIZE 0xe000
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#else
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#define PLAT_ARM_MAX_ROMLIB_RW_SIZE 0
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#define PLAT_ARM_MAX_ROMLIB_RO_SIZE 0
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#endif
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/*
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* PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a
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* little space for growth.
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*/
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#if TRUSTED_BOARD_BOOT
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# define PLAT_ARM_MAX_BL2_SIZE 0x1D000
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#else
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# define PLAT_ARM_MAX_BL2_SIZE 0x11000
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#endif
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/*
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* Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is
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* calculated using the current BL31 PROGBITS debug size plus the sizes of
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* BL2 and BL1-RW
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*/
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#define PLAT_ARM_MAX_BL31_SIZE 0x3B000
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/*
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* Size of cacheable stacks
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*/
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#if defined(IMAGE_BL1)
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# if TRUSTED_BOARD_BOOT
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# define PLATFORM_STACK_SIZE 0x1000
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# else
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# define PLATFORM_STACK_SIZE 0x440
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# endif
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#elif defined(IMAGE_BL2)
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# if TRUSTED_BOARD_BOOT
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# define PLATFORM_STACK_SIZE 0x1000
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# else
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# define PLATFORM_STACK_SIZE 0x400
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# endif
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#elif defined(IMAGE_BL2U)
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# define PLATFORM_STACK_SIZE 0x400
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#elif defined(IMAGE_BL31)
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# define PLATFORM_STACK_SIZE 0x400
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#elif defined(IMAGE_BL32)
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# define PLATFORM_STACK_SIZE 0x440
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#endif
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/*******************************************************************************
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* Memprotect definitions
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******************************************************************************/
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/* PSCI memory protect definitions:
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* This variable is stored in a non-secure flash because some ARM reference
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* platforms do not have secure NVRAM. Real systems that provided MEM_PROTECT
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* support must use a secure NVRAM to store the PSCI MEM_PROTECT definitions.
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*/
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#define PLAT_ARM_MEM_PROT_ADDR (V2M_FLASH0_BASE + \
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V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
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/* System power domain level */
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#define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2
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#endif /* SGM_BASE_PLATFORM_DEF_H */
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