233 lines
7.6 KiB
C
233 lines
7.6 KiB
C
/*
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* Copyright (C) 2016 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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#ifndef PLATFORM_DEF_H
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#define PLATFORM_DEF_H
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#ifndef __ASSEMBLER__
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#include <stdio.h>
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#endif /* __ASSEMBLER__ */
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#include <board_marvell_def.h>
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#include <mvebu_def.h>
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/*
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* Most platform porting definitions provided by included headers
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*/
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/*
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* DRAM Memory layout:
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* +-----------------------+
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* : :
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* : Linux :
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* 0x04X00000-->+-----------------------+
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* | BL3-3(u-boot) |>>}>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
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* |-----------------------| } |
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* | BL3-[0,1, 2] | }---------------------------------> |
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* |-----------------------| } || |
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* | BL2 | }->FIP (loaded by || |
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* |-----------------------| } BootROM to DRAM) || |
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* | FIP_TOC | } || |
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* 0x04120000-->|-----------------------| || |
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* | BL1 (RO) | || |
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* 0x04100000-->+-----------------------+ || |
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* : : || |
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* : Trusted SRAM section : \/ |
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* 0x04040000-->+-----------------------+ Replaced by BL2 +----------------+ |
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* | BL1 (RW) | <<<<<<<<<<<<<<<< | BL3-1 NOBITS | |
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* 0x04037000-->|-----------------------| <<<<<<<<<<<<<<<< |----------------| |
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* | | <<<<<<<<<<<<<<<< | BL3-1 PROGBITS | |
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* 0x04023000-->|-----------------------| +----------------+ |
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* | BL2 | |
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* |-----------------------| |
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* | | |
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* 0x04001000-->|-----------------------| |
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* | Shared | |
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* 0x04000000-->+-----------------------+ |
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* : : |
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* : Linux : |
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* : : |
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* |-----------------------| |
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* | | U-Boot(BL3-3) Loaded by BL2 |
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* | U-Boot | <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
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* 0x00000000-->+-----------------------+
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*
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* Trusted SRAM section 0x4000000..0x4200000:
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* ----------------------------------------
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* SRAM_BASE = 0x4001000
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* BL2_BASE = 0x4006000
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* BL2_LIMIT = BL31_BASE
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* BL31_BASE = 0x4023000 = (64MB + 256KB - 0x1D000)
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* BL31_PROGBITS_LIMIT = BL1_RW_BASE
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* BL1_RW_BASE = 0x4037000 = (64MB + 256KB - 0x9000)
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* BL1_RW_LIMIT = BL31_LIMIT = 0x4040000
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*
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*
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* PLAT_MARVELL_FIP_BASE = 0x4120000
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*/
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#define PLAT_MARVELL_ATF_BASE 0x4000000
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#define PLAT_MARVELL_ATF_LOAD_ADDR \
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(PLAT_MARVELL_ATF_BASE + 0x100000)
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#define PLAT_MARVELL_FIP_BASE \
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(PLAT_MARVELL_ATF_LOAD_ADDR + 0x20000)
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#define PLAT_MARVELL_FIP_MAX_SIZE 0x4000000
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#define PLAT_MARVELL_CLUSTER_CORE_COUNT 2
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/* DRAM[2MB..66MB] is used as Trusted ROM */
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#define PLAT_MARVELL_TRUSTED_ROM_BASE PLAT_MARVELL_ATF_LOAD_ADDR
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/* 64 MB TODO: reduce this to minimum needed according to fip image size*/
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#define PLAT_MARVELL_TRUSTED_ROM_SIZE 0x04000000
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/* Reserve 16M for SCP (Secure PayLoad) Trusted DRAM */
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#define PLAT_MARVELL_TRUSTED_DRAM_BASE 0x04400000
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#define PLAT_MARVELL_TRUSTED_DRAM_SIZE 0x01000000 /* 16 MB */
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/*
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* PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size
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* plus a little space for growth.
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*/
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#define PLAT_MARVELL_MAX_BL1_RW_SIZE 0xA000
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/*
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* PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a
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* little space for growth.
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*/
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#define PLAT_MARVELL_MAX_BL2_SIZE 0xF000
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/*
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* PLAT_ARM_MAX_BL31_SIZE is calculated using the current BL31 debug size plus a
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* little space for growth.
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*/
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#define PLAT_MARVEL_MAX_BL31_SIZE 0x5D000
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#define PLAT_MARVELL_CPU_ENTRY_ADDR BL1_RO_BASE
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/* GIC related definitions */
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#define PLAT_MARVELL_GICD_BASE (MVEBU_REGS_BASE + MVEBU_GICD_BASE)
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#define PLAT_MARVELL_GICR_BASE (MVEBU_REGS_BASE + MVEBU_GICR_BASE)
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#define PLAT_MARVELL_GICC_BASE (MVEBU_REGS_BASE + MVEBU_GICC_BASE)
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#define PLAT_MARVELL_G0_IRQ_PROPS(grp) \
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INTR_PROP_DESC(MARVELL_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_LEVEL), \
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INTR_PROP_DESC(MARVELL_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_LEVEL)
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#define PLAT_MARVELL_G1S_IRQ_PROPS(grp) \
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INTR_PROP_DESC(MARVELL_IRQ_SEC_PHY_TIMER, \
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GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \
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INTR_PROP_DESC(MARVELL_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_LEVEL), \
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INTR_PROP_DESC(MARVELL_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_LEVEL), \
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INTR_PROP_DESC(MARVELL_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_LEVEL), \
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INTR_PROP_DESC(MARVELL_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_LEVEL), \
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INTR_PROP_DESC(MARVELL_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_LEVEL), \
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INTR_PROP_DESC(MARVELL_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_LEVEL)
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#define PLAT_MARVELL_SHARED_RAM_CACHED 1
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/* CCI related constants */
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#define PLAT_MARVELL_CCI_BASE (MVEBU_REGS_BASE + MVEBU_CCI_BASE)
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#define PLAT_MARVELL_CCI_CLUSTER0_SL_IFACE_IX 3
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#define PLAT_MARVELL_CCI_CLUSTER1_SL_IFACE_IX 4
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/*
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* Load address of BL3-3 for this platform port
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*/
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#define PLAT_MARVELL_NS_IMAGE_OFFSET 0x0
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/* System Reference Clock*/
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#define PLAT_REF_CLK_IN_HZ COUNTER_FREQUENCY
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/*
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* PL011 related constants
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*/
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#define PLAT_MARVELL_BOOT_UART_BASE (MVEBU_REGS_BASE + 0x12000)
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#define PLAT_MARVELL_BOOT_UART_CLK_IN_HZ 25804800
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#define PLAT_MARVELL_CRASH_UART_BASE PLAT_MARVELL_BOOT_UART_BASE
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#define PLAT_MARVELL_CRASH_UART_CLK_IN_HZ PLAT_MARVELL_BOOT_UART_CLK_IN_HZ
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#define PLAT_MARVELL_BL31_RUN_UART_BASE PLAT_MARVELL_BOOT_UART_BASE
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#define PLAT_MARVELL_BL31_RUN_UART_CLK_IN_HZ PLAT_MARVELL_BOOT_UART_CLK_IN_HZ
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/* Required platform porting definitions */
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#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1
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/* System timer related constants */
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#define PLAT_MARVELL_NSTIMER_FRAME_ID 1
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/* Mailbox base address */
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#define PLAT_MARVELL_MAILBOX_BASE \
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(MARVELL_TRUSTED_SRAM_BASE + 0x400)
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#define PLAT_MARVELL_MAILBOX_SIZE 0x100
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#define PLAT_MARVELL_MAILBOX_MAGIC_NUM 0x6D72766C /* mrvl */
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/* DRAM CS memory map registers related constants */
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#define MVEBU_CS_MMAP_LOW(cs_num) \
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(MVEBU_CS_MMAP_REG_BASE + (cs_num) * 0x8)
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#define MVEBU_CS_MMAP_ENABLE 0x1
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#define MVEBU_CS_MMAP_AREA_LEN_OFFS 16
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#define MVEBU_CS_MMAP_AREA_LEN_MASK \
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(0x1f << MVEBU_CS_MMAP_AREA_LEN_OFFS)
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#define MVEBU_CS_MMAP_START_ADDR_LOW_OFFS 23
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#define MVEBU_CS_MMAP_START_ADDR_LOW_MASK \
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(0x1ff << MVEBU_CS_MMAP_START_ADDR_LOW_OFFS)
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#define MVEBU_CS_MMAP_HIGH(cs_num) \
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(MVEBU_CS_MMAP_REG_BASE + 0x4 + (cs_num) * 0x8)
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/* DRAM max CS number */
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#define MVEBU_MAX_CS_MMAP_NUM (2)
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/* CPU decoder window related constants */
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#define CPU_DEC_WIN_CTRL_REG(win_num) \
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(MVEBU_CPU_DEC_WIN_REG_BASE + (win_num) * 0x10)
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#define CPU_DEC_CR_WIN_ENABLE 0x1
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#define CPU_DEC_CR_WIN_TARGET_OFFS 4
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#define CPU_DEC_CR_WIN_TARGET_MASK \
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(0xf << CPU_DEC_CR_WIN_TARGET_OFFS)
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#define CPU_DEC_WIN_SIZE_REG(win_num) \
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(MVEBU_CPU_DEC_WIN_REG_BASE + 0x4 + (win_num) * 0x10)
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#define CPU_DEC_CR_WIN_SIZE_OFFS 0
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#define CPU_DEC_CR_WIN_SIZE_MASK \
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(0xffff << CPU_DEC_CR_WIN_SIZE_OFFS)
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#define CPU_DEC_CR_WIN_SIZE_ALIGNMENT 0x10000
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#define CPU_DEC_WIN_BASE_REG(win_num) \
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(MVEBU_CPU_DEC_WIN_REG_BASE + 0x8 + (win_num) * 0x10)
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#define CPU_DEC_BR_BASE_OFFS 0
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#define CPU_DEC_BR_BASE_MASK \
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(0xffff << CPU_DEC_BR_BASE_OFFS)
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#define CPU_DEC_REMAP_LOW_REG(win_num) \
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(MVEBU_CPU_DEC_WIN_REG_BASE + 0xC + (win_num) * 0x10)
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#define CPU_DEC_RLR_REMAP_LOW_OFFS 0
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#define CPU_DEC_RLR_REMAP_LOW_MASK \
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(0xffff << CPU_DEC_BR_BASE_OFFS)
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/* Securities */
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#define IRQ_SEC_OS_TICK_INT MARVELL_IRQ_SEC_PHY_TIMER
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#define TRUSTED_DRAM_BASE PLAT_MARVELL_TRUSTED_DRAM_BASE
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#define TRUSTED_DRAM_SIZE PLAT_MARVELL_TRUSTED_DRAM_SIZE
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#ifdef BL32
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#define BL32_BASE TRUSTED_DRAM_BASE
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#define BL32_LIMIT TRUSTED_DRAM_SIZE
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#endif
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#endif /* PLATFORM_DEF_H */
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