278 lines
5.5 KiB
C
278 lines
5.5 KiB
C
/*
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* Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#define BOARDNUM 2
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#define BOARD_JUDGE_AUTO
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#ifdef BOARD_JUDGE_AUTO
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static uint32_t _board_judge(uint32_t prr_product);
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static uint32_t boardcnf_get_brd_type(uint32_t prr_product)
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{
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return _board_judge(prr_product);
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}
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#else /* BOARD_JUDGE_AUTO */
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static uint32_t boardcnf_get_brd_type(void)
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{
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return 1U;
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}
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#endif /* BOARD_JUDGE_AUTO */
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#define DDR_FAST_INIT
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struct _boardcnf_ch {
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uint8_t ddr_density[CS_CNT];
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uint64_t ca_swap;
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uint16_t dqs_swap;
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uint32_t dq_swap[SLICE_CNT];
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uint8_t dm_swap[SLICE_CNT];
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uint16_t wdqlvl_patt[16];
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int8_t cacs_adj[16];
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int8_t dm_adj_w[SLICE_CNT];
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int8_t dq_adj_w[SLICE_CNT * 8U];
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int8_t dm_adj_r[SLICE_CNT];
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int8_t dq_adj_r[SLICE_CNT * 8U];
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};
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struct _boardcnf {
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uint8_t phyvalid;
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uint8_t dbi_en;
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uint16_t cacs_dly;
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int16_t cacs_dly_adj;
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uint16_t dqdm_dly_w;
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uint16_t dqdm_dly_r;
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struct _boardcnf_ch ch[DRAM_CH_CNT];
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};
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#define WDQLVL_PAT {\
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0x00AA,\
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0x0055,\
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0x00AA,\
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0x0155,\
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0x01CC,\
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0x0133,\
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0x00CC,\
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0x0033,\
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0x00F0,\
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0x010F,\
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0x01F0,\
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0x010F,\
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0x00F0,\
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0x00F0,\
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0x000F,\
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0x010F}
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static const struct _boardcnf boardcnfs[BOARDNUM] = {
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{
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/* boardcnf[0] HopeRun HiHope RZ/G2M 16Gbit/1rank/2ch board with G2M SoC */
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.phyvalid = 0x03,
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.dbi_en = 0x01,
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.cacs_dly = 0x02c0,
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.cacs_dly_adj = 0,
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.dqdm_dly_w = 0x0300,
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.dqdm_dly_r = 0x00a0,
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.ch = {
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{
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{0x04, 0xff},
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0x00345201U,
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0x3201,
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{0x01672543U, 0x45361207U, 0x45632107U, 0x60715234U},
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{0x08, 0x08, 0x08, 0x08},
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WDQLVL_PAT,
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{0, 0, 0, 0, 0, 0, 0, 0,
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0, 0},
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{0, 0, 0, 0},
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{0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0},
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{0, 0, 0, 0},
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{0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0}
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},
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{
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{0x04, 0xff},
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0x00302154U,
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0x2310,
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{0x01672543U, 0x45361207U, 0x45632107U, 0x60715234U},
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{0x08, 0x08, 0x08, 0x08},
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WDQLVL_PAT,
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{0, 0, 0, 0, 0, 0, 0, 0,
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0, 0},
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{0, 0, 0, 0},
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{0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0},
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{0, 0, 0, 0},
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{0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0}
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}
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}
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},
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/* boardcnf[1] HopeRun HiHope RZ/G2M 8Gbit/2rank/2ch board with G2M SoC */
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{
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0x03,
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0x01,
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0x02c0,
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0,
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0x0300,
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0x00a0,
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{
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{
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{0x02, 0x02},
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0x00345201U,
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0x3201,
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{0x01672543U, 0x45361207U, 0x45632107U, 0x60715234U},
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{0x08, 0x08, 0x08, 0x08},
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WDQLVL_PAT,
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{0, 0, 0, 0, 0, 0, 0, 0,
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0, 0},
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{0, 0, 0, 0},
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{0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0},
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{0, 0, 0, 0},
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{0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0}
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},
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{
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{0x02, 0x02},
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0x00302154U,
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0x2310,
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{0x01672543U, 0x45361207U, 0x45632107U, 0x60715234U},
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{0x08, 0x08, 0x08, 0x08},
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WDQLVL_PAT,
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{0, 0, 0, 0, 0, 0, 0, 0,
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0, 0},
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{0, 0, 0, 0},
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{0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0},
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{0, 0, 0, 0},
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{0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0}
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}
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}
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}
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};
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void boardcnf_get_brd_clk(uint32_t brd, uint32_t *clk, uint32_t *div)
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{
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uint32_t md;
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md = (mmio_read_32(RST_MODEMR) >> 13) & 0x3U;
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switch (md) {
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case 0x0U:
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*clk = 50U;
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*div = 3U;
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break;
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case 0x1U:
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*clk = 60U;
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*div = 3U;
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break;
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case 0x2U:
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*clk = 75U;
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*div = 3U;
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break;
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case 0x3U:
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*clk = 100U;
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*div = 3U;
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break;
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default:
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break;
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}
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(void)brd;
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}
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void boardcnf_get_ddr_mbps(uint32_t brd, uint32_t *mbps, uint32_t *div)
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{
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uint32_t md;
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md = (mmio_read_32(RST_MODEMR) >> 17U) & 0x5U;
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md = (md | (md >> 1U)) & 0x3U;
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switch (md) {
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case 0x0U:
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*mbps = 3200U;
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*div = 1U;
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break;
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case 0x1U:
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*mbps = 2800U;
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*div = 1U;
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break;
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case 0x2U:
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*mbps = 2400U;
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*div = 1U;
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break;
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case 0x3U:
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*mbps = 1600U;
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*div = 1U;
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break;
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default:
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break;
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}
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(void)brd;
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}
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#define _def_REFPERIOD 1890
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#define M3_SAMPLE_TT_A84 0xB866CC10U, 0x3B250421U
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#define M3_SAMPLE_TT_A85 0xB866CC10U, 0x3AA50421U
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#define M3_SAMPLE_TT_A86 0xB866CC10U, 0x3AA48421U
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#define M3_SAMPLE_FF_B45 0xB866CC10U, 0x3AB00C21U
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#define M3_SAMPLE_FF_B49 0xB866CC10U, 0x39B10C21U
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#define M3_SAMPLE_FF_B56 0xB866CC10U, 0x3AAF8C21U
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#define M3_SAMPLE_SS_E24 0xB866CC10U, 0x3BA39421U
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#define M3_SAMPLE_SS_E28 0xB866CC10U, 0x3C231421U
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#define M3_SAMPLE_SS_E32 0xB866CC10U, 0x3C241421U
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static const uint32_t termcode_by_sample[20][3] = {
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{ M3_SAMPLE_TT_A84, 0x000158D5U },
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{ M3_SAMPLE_TT_A85, 0x00015955U },
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{ M3_SAMPLE_TT_A86, 0x00015955U },
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{ M3_SAMPLE_FF_B45, 0x00015690U },
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{ M3_SAMPLE_FF_B49, 0x00015753U },
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{ M3_SAMPLE_FF_B56, 0x00015793U },
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{ M3_SAMPLE_SS_E24, 0x00015996U },
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{ M3_SAMPLE_SS_E28, 0x000159D7U },
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{ M3_SAMPLE_SS_E32, 0x00015997U },
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{ 0xFFFFFFFFU, 0xFFFFFFFFU, 0x0001554FU}
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};
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#ifdef BOARD_JUDGE_AUTO
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/* Board detect function */
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#define GPIO_INDT5 0xE605500CU
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#define LPDDR4_2RANK (0x01U << 25U)
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static uint32_t _board_judge(uint32_t prr_product)
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{
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uint32_t boardInfo;
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uint32_t boardid = 1U;
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if (prr_product == PRR_PRODUCT_M3) {
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if ((mmio_read_32(PRR) & PRR_CUT_MASK) != RCAR_M3_CUT_VER11) {
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boardInfo = mmio_read_32(GPIO_INDT5);
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if ((boardInfo & LPDDR4_2RANK) == 0U) {
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boardid = 0U;
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}
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}
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}
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return boardid;
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}
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#endif /* BOARD_JUDGE_AUTO */
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