68 lines
1.8 KiB
ArmAsm
68 lines
1.8 KiB
ArmAsm
/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <platform_def.h>
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.globl plat_is_my_cpu_primary
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.globl plat_arm_calc_core_pos
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/* -----------------------------------------------------
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* unsigned int plat_is_my_cpu_primary (void);
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*
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* Find out whether the current cpu is the primary
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* cpu (applicable only after a cold boot)
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* -----------------------------------------------------
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*/
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func plat_is_my_cpu_primary
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mov x9, x30
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bl plat_my_core_pos
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ldr x1, =SGI_BOOT_CFG_ADDR
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ldr x1, [x1]
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ubfx x1, x1, #PLAT_CSS_PRIMARY_CPU_SHIFT, \
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#PLAT_CSS_PRIMARY_CPU_BIT_WIDTH
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cmp x0, x1
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cset w0, eq
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ret x9
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endfunc plat_is_my_cpu_primary
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/* -----------------------------------------------------
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* unsigned int plat_arm_calc_core_pos(u_register_t mpidr)
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*
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* Helper function to calculate the core position.
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* (ClusterId * CSS_SGI_MAX_CPUS_PER_CLUSTER * CSS_SGI_MAX_PE_PER_CPU) +
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* (CPUId * CSS_SGI_MAX_PE_PER_CPU) +
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* ThreadId
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*
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* which can be simplified as:
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*
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* ((ClusterId * CSS_SGI_MAX_CPUS_PER_CLUSTER + CPUId) *
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* CSS_SGI_MAX_PE_PER_CPU) + ThreadId
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* ------------------------------------------------------
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*/
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func plat_arm_calc_core_pos
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mov x3, x0
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/*
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* The MT bit in MPIDR is always set for SGI platforms
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* and the affinity level 0 corresponds to thread affinity level.
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*/
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/* Extract individual affinity fields from MPIDR */
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ubfx x0, x3, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
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ubfx x1, x3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
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ubfx x2, x3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
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/* Compute linear position */
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mov x4, #CSS_SGI_MAX_CPUS_PER_CLUSTER
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madd x1, x2, x4, x1
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mov x5, #CSS_SGI_MAX_PE_PER_CPU
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madd x0, x1, x5, x0
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ret
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endfunc plat_arm_calc_core_pos
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