219 lines
5.2 KiB
ArmAsm
219 lines
5.2 KiB
ArmAsm
/*
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* Copyright (c) 2020, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <context.h>
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#include <cpu_macros.S>
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#include <cpuamu.h>
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#include <rainier.h>
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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#error "Rainier CPU must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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/* 64-bit only core */
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#if CTX_INCLUDE_AARCH32_REGS == 1
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#error "Rainier CPU supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
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#endif
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#if ERRATA_RAINIER_IC_TRAP
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.global rainier_errata_ic_trap_handler
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#endif
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/* --------------------------------------------------
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* Disable speculative loads if Rainier supports
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* SSBS.
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*
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* Shall clobber: x0.
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* --------------------------------------------------
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*/
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func rainier_disable_speculative_loads
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/* Check if the PE implements SSBS */
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mrs x0, id_aa64pfr1_el1
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tst x0, #(ID_AA64PFR1_EL1_SSBS_MASK << ID_AA64PFR1_EL1_SSBS_SHIFT)
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b.eq 1f
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/* Disable speculative loads */
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msr SSBS, xzr
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1:
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ret
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endfunc rainier_disable_speculative_loads
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/* --------------------------------------------------
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* Errata Workaround for Neoverse N1 Erratum 1542419.
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* This applies to revisions r3p0 - r4p0 of Neoverse N1
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* Since Rainier core is based on Neoverse N1 r4p0, this
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* errata applies to Rainier core r0p0
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_n1_1542419_wa
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/* Compare x0 against revision r3p0 and r4p0 */
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mov x17, x30
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bl check_errata_1542419
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cbz x0, 1f
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/* Apply instruction patching sequence */
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mov x0, xzr
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msr CPUPSELR_EL3, x0
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ldr x0, =0xEE670D35
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msr CPUPOR_EL3, x0
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ldr x0, =0xFFFF0FFF
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msr CPUPMR_EL3, x0
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ldr x0, =0x08000020007D
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msr CPUPCR_EL3, x0
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isb
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1:
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ret x17
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endfunc errata_n1_1542419_wa
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func check_errata_1542419
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/* Applies to Rainier core r0p0. */
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mov x1, #0x00
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b cpu_rev_var_ls
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endfunc check_errata_1542419
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func rainier_reset_func
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mov x19, x30
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bl rainier_disable_speculative_loads
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/* Forces all cacheable atomic instructions to be near */
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mrs x0, RAINIER_CPUACTLR2_EL1
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orr x0, x0, #RAINIER_CPUACTLR2_EL1_BIT_2
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msr RAINIER_CPUACTLR2_EL1, x0
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isb
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bl cpu_get_rev_var
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mov x18, x0
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#if ERRATA_N1_1542419
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mov x0, x18
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bl errata_n1_1542419_wa
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#endif
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#if ENABLE_AMU
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/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
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mrs x0, actlr_el3
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orr x0, x0, #RAINIER_ACTLR_AMEN_BIT
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msr actlr_el3, x0
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/* Make sure accesses from EL0/EL1 are not trapped to EL2 */
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mrs x0, actlr_el2
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orr x0, x0, #RAINIER_ACTLR_AMEN_BIT
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msr actlr_el2, x0
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/* Enable group0 counters */
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mov x0, #RAINIER_AMU_GROUP0_MASK
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msr CPUAMCNTENSET_EL0, x0
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#endif
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isb
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ret x19
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endfunc rainier_reset_func
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/* ---------------------------------------------
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* HW will do the cache maintenance while powering down
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* ---------------------------------------------
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*/
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func rainier_core_pwr_dwn
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/* ---------------------------------------------
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* Enable CPU power down bit in power control register
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* ---------------------------------------------
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*/
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mrs x0, RAINIER_CPUPWRCTLR_EL1
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orr x0, x0, #RAINIER_CORE_PWRDN_EN_MASK
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msr RAINIER_CPUPWRCTLR_EL1, x0
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isb
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ret
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endfunc rainier_core_pwr_dwn
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#if REPORT_ERRATA
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/*
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* Errata printing function for Rainier. Must follow AAPCS.
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*/
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func rainier_errata_report
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stp x8, x30, [sp, #-16]!
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bl cpu_get_rev_var
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mov x8, x0
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/*
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* Report all errata. The revision-variant information is passed to
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* checking functions of each errata.
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*/
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report_errata ERRATA_N1_1542419, rainier, 1542419
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ldp x8, x30, [sp], #16
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ret
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endfunc rainier_errata_report
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#endif
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/*
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* Handle trap of EL0 IC IVAU instructions to EL3 by executing a TLB
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* inner-shareable invalidation to an arbitrary address followed by a DSB.
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*
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* x1: Exception Syndrome
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*/
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func rainier_errata_ic_trap_handler
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cmp x1, #RAINIER_EC_IC_TRAP
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b.ne 1f
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tlbi vae3is, xzr
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dsb sy
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# Skip the IC instruction itself
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mrs x3, elr_el3
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add x3, x3, #4
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msr elr_el3, x3
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ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
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ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
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ldp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4]
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ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
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#if IMAGE_BL31 && RAS_EXTENSION
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/*
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* Issue Error Synchronization Barrier to synchronize SErrors before
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* exiting EL3. We're running with EAs unmasked, so any synchronized
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* errors would be taken immediately; therefore no need to inspect
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* DISR_EL1 register.
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*/
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esb
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#endif
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eret
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1:
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ret
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endfunc rainier_errata_ic_trap_handler
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/* ---------------------------------------------
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* This function provides Rainier specific
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* register information for crash reporting.
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* It needs to return with x6 pointing to
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* a list of register names in ascii and
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* x8 - x15 having values of registers to be
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* reported.
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* ---------------------------------------------
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*/
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.section .rodata.rainier_regs, "aS"
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rainier_regs: /* The ascii list of register names to be reported */
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.asciz "cpuectlr_el1", ""
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func rainier_cpu_reg_dump
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adr x6, rainier_regs
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mrs x8, RAINIER_CPUECTLR_EL1
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ret
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endfunc rainier_cpu_reg_dump
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declare_cpu_ops_eh rainier, RAINIER_MIDR, \
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rainier_reset_func, \
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rainier_errata_ic_trap_handler, \
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rainier_core_pwr_dwn
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