330 lines
8.6 KiB
C
330 lines
8.6 KiB
C
/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __SOC_ROCKCHIP_RK3399_SDRAM_H__
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#define __SOC_ROCKCHIP_RK3399_SDRAM_H__
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struct rk3399_ddr_cic_regs {
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uint32_t cic_ctrl0;
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uint32_t cic_ctrl1;
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uint32_t cic_idle_th;
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uint32_t cic_cg_wait_th;
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uint32_t cic_status0;
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uint32_t cic_status1;
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uint32_t cic_ctrl2;
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uint32_t cic_ctrl3;
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uint32_t cic_ctrl4;
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};
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/* DENALI_CTL_00 */
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#define START (1)
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/* DENALI_CTL_68 */
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#define PWRUP_SREFRESH_EXIT (1 << 16)
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/* DENALI_CTL_274 */
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#define MEM_RST_VALID (1)
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struct rk3399_ddr_pctl_regs {
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uint32_t denali_ctl[332];
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};
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struct rk3399_ddr_publ_regs {
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uint32_t denali_phy[959];
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};
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#define PHY_DRV_ODT_Hi_Z (0x0)
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#define PHY_DRV_ODT_240 (0x1)
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#define PHY_DRV_ODT_120 (0x8)
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#define PHY_DRV_ODT_80 (0x9)
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#define PHY_DRV_ODT_60 (0xc)
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#define PHY_DRV_ODT_48 (0xd)
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#define PHY_DRV_ODT_40 (0xe)
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#define PHY_DRV_ODT_34_3 (0xf)
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struct rk3399_ddr_pi_regs {
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uint32_t denali_pi[200];
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};
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union noc_ddrtiminga0 {
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uint32_t d32;
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struct {
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unsigned acttoact : 6;
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unsigned reserved0 : 2;
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unsigned rdtomiss : 6;
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unsigned reserved1 : 2;
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unsigned wrtomiss : 6;
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unsigned reserved2 : 2;
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unsigned readlatency : 8;
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} b;
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};
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union noc_ddrtimingb0 {
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uint32_t d32;
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struct {
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unsigned rdtowr : 5;
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unsigned reserved0 : 3;
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unsigned wrtord : 5;
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unsigned reserved1 : 3;
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unsigned rrd : 4;
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unsigned reserved2 : 4;
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unsigned faw : 6;
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unsigned reserved3 : 2;
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} b;
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};
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union noc_ddrtimingc0 {
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uint32_t d32;
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struct {
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unsigned burstpenalty : 4;
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unsigned reserved0 : 4;
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unsigned wrtomwr : 6;
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unsigned reserved1 : 18;
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} b;
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};
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union noc_devtodev0 {
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uint32_t d32;
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struct {
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unsigned busrdtord : 3;
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unsigned reserved0 : 1;
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unsigned busrdtowr : 3;
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unsigned reserved1 : 1;
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unsigned buswrtord : 3;
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unsigned reserved2 : 1;
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unsigned buswrtowr : 3;
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unsigned reserved3 : 17;
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} b;
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};
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union noc_ddrmode {
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uint32_t d32;
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struct {
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unsigned autoprecharge : 1;
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unsigned bypassfiltering : 1;
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unsigned fawbank : 1;
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unsigned burstsize : 2;
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unsigned mwrsize : 2;
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unsigned reserved2 : 1;
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unsigned forceorder : 8;
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unsigned forceorderstate : 8;
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unsigned reserved3 : 8;
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} b;
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};
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struct rk3399_msch_regs {
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uint32_t coreid;
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uint32_t revisionid;
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uint32_t ddrconf;
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uint32_t ddrsize;
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union noc_ddrtiminga0 ddrtiminga0;
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union noc_ddrtimingb0 ddrtimingb0;
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union noc_ddrtimingc0 ddrtimingc0;
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union noc_devtodev0 devtodev0;
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uint32_t reserved0[(0x110-0x20)/4];
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union noc_ddrmode ddrmode;
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uint32_t reserved1[(0x1000-0x114)/4];
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uint32_t agingx0;
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};
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struct rk3399_msch_timings {
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union noc_ddrtiminga0 ddrtiminga0;
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union noc_ddrtimingb0 ddrtimingb0;
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union noc_ddrtimingc0 ddrtimingc0;
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union noc_devtodev0 devtodev0;
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union noc_ddrmode ddrmode;
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uint32_t agingx0;
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};
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#if 1
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struct rk3399_sdram_channel {
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unsigned char rank;
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/* col = 0, means this channel is invalid */
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unsigned char col;
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/* 3:8bank, 2:4bank */
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unsigned char bk;
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/* channel buswidth, 2:32bit, 1:16bit, 0:8bit */
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unsigned char bw;
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/* die buswidth, 2:32bit, 1:16bit, 0:8bit */
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unsigned char dbw;
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/* row_3_4 = 1: 6Gb or 12Gb die
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* row_3_4 = 0: normal die, power of 2
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*/
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unsigned char row_3_4;
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unsigned char cs0_row;
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unsigned char cs1_row;
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uint32_t ddrconfig;
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struct rk3399_msch_timings noc_timings;
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};
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struct rk3399_sdram_params {
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struct rk3399_sdram_channel ch[2];
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uint32_t ddr_freq;
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unsigned char dramtype;
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unsigned char num_channels;
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unsigned char stride;
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unsigned char odt;
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struct rk3399_ddr_pctl_regs pctl_regs;
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struct rk3399_ddr_pi_regs pi_regs;
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struct rk3399_ddr_publ_regs phy_regs;
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};
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#endif
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struct rk3399_sdram_channel_config {
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uint32_t bus_width;
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uint32_t cs_cnt;
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uint32_t cs0_row;
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uint32_t cs1_row;
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uint32_t bank;
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uint32_t col;
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uint32_t each_die_bus_width;
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uint32_t each_die_6gb_or_12gb;
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};
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struct rk3399_sdram_config {
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struct rk3399_sdram_channel_config ch[2];
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uint32_t dramtype;
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uint32_t channal_num;
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};
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struct rk3399_sdram_default_config {
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unsigned char bl;
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/* 1:auto precharge, 0:never auto precharge */
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unsigned char ap;
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/* dram driver strength */
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unsigned char dramds;
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/* dram ODT, if odt=0, this parameter invalid */
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unsigned char dramodt;
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/* ca ODT, if odt=0, this parameter invalid
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* only used by LPDDR4
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*/
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unsigned char caodt;
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unsigned char burst_ref_cnt;
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/* zqcs period, unit(s) */
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unsigned char zqcsi;
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};
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struct ddr_dts_config_timing {
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unsigned int ddr3_speed_bin;
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unsigned int pd_idle;
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unsigned int sr_idle;
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unsigned int sr_mc_gate_idle;
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unsigned int srpd_lite_idle;
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unsigned int standby_idle;
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unsigned int auto_pd_dis_freq;
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unsigned int ddr3_dll_dis_freq;
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unsigned int phy_dll_dis_freq;
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unsigned int ddr3_odt_dis_freq;
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unsigned int ddr3_drv;
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unsigned int ddr3_odt;
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unsigned int phy_ddr3_ca_drv;
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unsigned int phy_ddr3_dq_drv;
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unsigned int phy_ddr3_odt;
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unsigned int lpddr3_odt_dis_freq;
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unsigned int lpddr3_drv;
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unsigned int lpddr3_odt;
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unsigned int phy_lpddr3_ca_drv;
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unsigned int phy_lpddr3_dq_drv;
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unsigned int phy_lpddr3_odt;
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unsigned int lpddr4_odt_dis_freq;
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unsigned int lpddr4_drv;
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unsigned int lpddr4_dq_odt;
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unsigned int lpddr4_ca_odt;
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unsigned int phy_lpddr4_ca_drv;
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unsigned int phy_lpddr4_ck_cs_drv;
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unsigned int phy_lpddr4_dq_drv;
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unsigned int phy_lpddr4_odt;
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uint32_t available;
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};
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struct drv_odt_lp_config {
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uint32_t ddr3_speed_bin;
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uint32_t pd_idle;
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uint32_t sr_idle;
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uint32_t sr_mc_gate_idle;
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uint32_t srpd_lite_idle;
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uint32_t standby_idle;
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uint32_t ddr3_dll_dis_freq;/* for ddr3 only */
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uint32_t phy_dll_dis_freq;
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uint32_t odt_dis_freq;
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uint32_t dram_side_drv;
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uint32_t dram_side_dq_odt;
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uint32_t dram_side_ca_odt;
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uint32_t phy_side_ca_drv;
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uint32_t phy_side_ck_cs_drv;
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uint32_t phy_side_dq_drv;
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uint32_t phy_side_odt;
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};
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#define KHz (1000)
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#define MHz (1000*KHz)
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#define GHz (1000*MHz)
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#define PI_CA_TRAINING (1 << 0)
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#define PI_WRITE_LEVELING (1 << 1)
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#define PI_READ_GATE_TRAINING (1 << 2)
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#define PI_READ_LEVELING (1 << 3)
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#define PI_WDQ_LEVELING (1 << 4)
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#define PI_FULL_TARINING (0xff)
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#define READ_CH_CNT(val) (1+((val>>12)&0x1))
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#define READ_CH_INFO(val) ((val>>28)&0x3)
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/* row_3_4:0=normal, 1=6Gb or 12Gb */
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#define READ_CH_ROW_INFO(val, ch) ((val>>(30+(ch)))&0x1)
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#define READ_DRAMTYPE_INFO(val) ((val>>13)&0x7)
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#define READ_CS_INFO(val, ch) ((((val)>>(11+(ch)*16))&0x1)+1)
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#define READ_BW_INFO(val, ch) (2>>(((val)>>(2+(ch)*16))&0x3))
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#define READ_COL_INFO(val, ch) (9+(((val)>>(9+(ch)*16))&0x3))
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#define READ_BK_INFO(val, ch) (3-(((val)>>(8+(ch)*16))&0x1))
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#define READ_CS0_ROW_INFO(val, ch) (13+(((val)>>(6+(ch)*16))&0x3))
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#define READ_CS1_ROW_INFO(val, ch) (13+(((val)>>(4+(ch)*16))&0x3))
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#define READ_DIE_BW_INFO(val, ch) (2>>((val>>((ch)*16))&0x3))
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#define __sramdata __attribute__((section(".sram.data")))
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#define __sramconst __attribute__((section(".sram.rodata")))
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#define __sramlocalfunc __attribute__((section(".sram.text")))
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#define __sramfunc __attribute__((section(".sram.text"))) \
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__attribute__((noinline))
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#define DDR_SAVE_SP(save_sp) (save_sp = ddr_save_sp(((uint32_t)\
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(SRAM_CODE_BASE + 0x2000) & (~7))))
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#define DDR_RESTORE_SP(save_sp) ddr_save_sp(save_sp)
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void ddr_init(void);
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uint32_t ddr_set_rate(uint32_t hz);
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uint32_t ddr_round_rate(uint32_t hz);
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uint32_t ddr_get_rate(void);
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void clr_dcf_irq(void);
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uint32_t dts_timing_receive(uint32_t timing, uint32_t index);
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#endif
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