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A TZC400 controller is placed inline on DRAM channels and regulates the secure and non-secure accesses to both secure and non-secure regions of the DRAM memory. Configure each of the TZC controllers across the Chips. For use by secure software, configure the first chip's trustzone controller to protect the upper 16MB of the memory of the first DRAM block for secure accesses only. The other regions are configured for non-secure read write access. For all the remote chips, all the DRAM regions are allowed for non-secure read and write access. Signed-off-by: Aditya Angadi <aditya.angadi@arm.com> Change-Id: I809f27eccadfc23ea0ef64e2fd87f95eb8f195c1 |
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| .. | ||
| fdts | ||
| include | ||
| platform.mk | ||
| rdv1mc_err.c | ||
| rdv1mc_plat.c | ||
| rdv1mc_security.c | ||
| rdv1mc_topology.c | ||
| rdv1mc_trusted_boot.c | ||