248 lines
8.0 KiB
C
248 lines
8.0 KiB
C
/*
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* Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __JUNO_DEF_H__
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#define __JUNO_DEF_H__
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/* Special value used to verify platform parameters from BL2 to BL3-1 */
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#define JUNO_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL
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/*******************************************************************************
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* Juno memory map related constants
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******************************************************************************/
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#define FLASH_BASE 0x08000000
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#define FLASH_SIZE 0x04000000
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/* Bypass offset from start of NOR flash */
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#define BL1_ROM_BYPASS_OFFSET 0x03EC0000
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#ifndef TZROM_BASE
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/* Use the bypass address */
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#define TZROM_BASE FLASH_BASE + BL1_ROM_BYPASS_OFFSET
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#endif
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/* Actual ROM size on Juno is 64 KB, but TBB requires at least 80 KB in debug
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* mode. We can test TBB on Juno bypassing the ROM and using 128 KB of flash */
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#if TRUSTED_BOARD_BOOT
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#define TZROM_SIZE 0x00020000
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#else
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#define TZROM_SIZE 0x00010000
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#endif
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#define TZRAM_BASE 0x04001000
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#define TZRAM_SIZE 0x0003F000
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#define PLAT_TRUSTED_SRAM_ID 0
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#define PLAT_DRAM_ID 1
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#define MHU_SECURE_BASE 0x04000000
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#define MHU_SECURE_SIZE 0x00001000
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#define MHU_PAYLOAD_CACHED 0
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#define TRUSTED_MAILBOXES_BASE MHU_SECURE_BASE
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#define TRUSTED_MAILBOX_SHIFT 4
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#define EMMC_BASE 0x0c000000
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#define EMMC_SIZE 0x04000000
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#define PSRAM_BASE 0x14000000
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#define PSRAM_SIZE 0x02000000
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#define IOFPGA_BASE 0x1c000000
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#define IOFPGA_SIZE 0x03000000
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#define NSROM_BASE 0x1f000000
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#define NSROM_SIZE 0x00001000
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/* Following covers Columbus Peripherals excluding NSROM and NSRAM */
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#define DEVICE0_BASE 0x20000000
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#define DEVICE0_SIZE 0x0e000000
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#define MHU_BASE 0x2b1f0000
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#define NSRAM_BASE 0x2e000000
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#define NSRAM_SIZE 0x00008000
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/* Following covers Juno Peripherals and PCIe expansion area */
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#define DEVICE1_BASE 0x40000000
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#define DEVICE1_SIZE 0x40000000
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#define PCIE_CONTROL_BASE 0x7ff20000
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#define DRAM_BASE 0x80000000
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#define DRAM_SIZE 0x80000000
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/*
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* DRAM at 0x8000_0000 is divided in two regions:
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* - Secure DRAM (default is the top 16MB except for the last 2MB, which are
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* used by the SCP for DDR retraining)
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* - Non-Secure DRAM (remaining DRAM starting at DRAM_BASE)
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*/
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#define DRAM_SCP_SIZE 0x00200000
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#define DRAM_SCP_BASE (DRAM_BASE + DRAM_SIZE - DRAM_SCP_SIZE)
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#define DRAM_SEC_SIZE 0x00E00000
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#define DRAM_SEC_BASE (DRAM_SCP_BASE - DRAM_SEC_SIZE)
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#define DRAM_NS_BASE DRAM_BASE
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#define DRAM_NS_SIZE (DRAM_SIZE - DRAM_SCP_SIZE - DRAM_SEC_SIZE)
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/* Second region of DRAM */
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#define DRAM2_BASE 0x880000000
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#define DRAM2_SIZE 0x180000000
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/* Memory mapped Generic timer interfaces */
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#define SYS_CNTCTL_BASE 0x2a430000
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#define SYS_CNTREAD_BASE 0x2a800000
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#define SYS_TIMCTL_BASE 0x2a810000
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/* V2M motherboard system registers & offsets */
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#define VE_SYSREGS_BASE 0x1c010000
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#define V2M_SYS_LED 0x8
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/*
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* V2M sysled bit definitions. The values written to this
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* register are defined in arch.h & runtime_svc.h. Only
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* used by the primary cpu to diagnose any cold boot issues.
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*
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* SYS_LED[0] - Security state (S=0/NS=1)
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* SYS_LED[2:1] - Exception Level (EL3-EL0)
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* SYS_LED[7:3] - Exception Class (Sync/Async & origin)
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*
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*/
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#define SYS_LED_SS_SHIFT 0x0
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#define SYS_LED_EL_SHIFT 0x1
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#define SYS_LED_EC_SHIFT 0x3
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/*******************************************************************************
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* GIC-400 & interrupt handling related constants
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******************************************************************************/
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#define GICD_BASE 0x2c010000
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#define GICC_BASE 0x2c02f000
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#define GICH_BASE 0x2c04f000
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#define GICV_BASE 0x2c06f000
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#define IRQ_MHU 69
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#define IRQ_GPU_SMMU_0 71
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#define IRQ_GPU_SMMU_1 73
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#define IRQ_ETR_SMMU 75
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#define IRQ_TZC400 80
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#define IRQ_TZ_WDOG 86
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#define IRQ_SEC_PHY_TIMER 29
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#define IRQ_SEC_SGI_0 8
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#define IRQ_SEC_SGI_1 9
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#define IRQ_SEC_SGI_2 10
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#define IRQ_SEC_SGI_3 11
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#define IRQ_SEC_SGI_4 12
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#define IRQ_SEC_SGI_5 13
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#define IRQ_SEC_SGI_6 14
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#define IRQ_SEC_SGI_7 15
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/*******************************************************************************
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* PL011 related constants
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******************************************************************************/
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/* FPGA UART0 */
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#define PL011_UART0_BASE 0x1c090000
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/* FPGA UART1 */
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#define PL011_UART1_BASE 0x1c0a0000
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/* SoC UART0 */
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#define PL011_UART2_BASE 0x7ff80000
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/* SoC UART1 */
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#define PL011_UART3_BASE 0x7ff70000
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#define PL011_BAUDRATE 115200
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#define PL011_UART0_CLK_IN_HZ 24000000
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#define PL011_UART1_CLK_IN_HZ 24000000
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#define PL011_UART2_CLK_IN_HZ 7273800
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#define PL011_UART3_CLK_IN_HZ 7273800
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/*******************************************************************************
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* NIC-400 related constants
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******************************************************************************/
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/* CSS NIC-400 Global Programmers View (GPV) */
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#define CSS_NIC400_BASE 0x2a000000
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/* The slave_bootsecure controls access to GPU, DMC and CS. */
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#define CSS_NIC400_SLAVE_BOOTSECURE 8
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/* SoC NIC-400 Global Programmers View (GPV) */
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#define SOC_NIC400_BASE 0x7fd00000
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#define SOC_NIC400_USB_EHCI 0
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#define SOC_NIC400_TLX_MASTER 1
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#define SOC_NIC400_USB_OHCI 2
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#define SOC_NIC400_PL354_SMC 3
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/*
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* The apb4_bridge controls access to:
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* - the PCIe configuration registers
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* - the MMU units for USB, HDLCD and DMA
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*/
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#define SOC_NIC400_APB4_BRIDGE 4
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/*
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* The bootsec_bridge controls access to a bunch of peripherals, e.g. the UARTs.
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*/
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#define SOC_NIC400_BOOTSEC_BRIDGE 5
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#define SOC_NIC400_BOOTSEC_BRIDGE_UART1 (1 << 12)
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/*******************************************************************************
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* TZC-400 related constants
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******************************************************************************/
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#define TZC400_BASE 0x2a4a0000
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#define TZC400_NSAID_CCI400 0 /* Note: Same as default NSAID!! */
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#define TZC400_NSAID_PCIE 1
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#define TZC400_NSAID_HDLCD0 2
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#define TZC400_NSAID_HDLCD1 3
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#define TZC400_NSAID_USB 4
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#define TZC400_NSAID_DMA330 5
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#define TZC400_NSAID_THINLINKS 6
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#define TZC400_NSAID_AP 9
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#define TZC400_NSAID_GPU 10
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#define TZC400_NSAID_SCP 11
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#define TZC400_NSAID_CORESIGHT 12
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/*******************************************************************************
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* CCI-400 related constants
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******************************************************************************/
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#define CCI400_BASE 0x2c090000
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#define CCI400_SL_IFACE3_CLUSTER_IX 1
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#define CCI400_SL_IFACE4_CLUSTER_IX 0
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/*******************************************************************************
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* SCP <=> AP boot configuration
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******************************************************************************/
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#define SCP_BOOT_CFG_ADDR 0x04000080
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#define PRIMARY_CPU_SHIFT 8
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#define PRIMARY_CPU_MASK 0xf
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#endif /* __JUNO_DEF_H__ */
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