Varun Wadekar db891f32f6 Tegra194: access XUSB_PADCTL registers on Si/FPGA platforms ... Many simulation/emulation platforms do not support this hardware block leading to SErrors during register accesses. This patch conditionally accesses the registers from this block only on actual Si and FPGA platforms. Change-Id: Ic22817a8c9f81978ba88c5362bfd734a0040d35d Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>		2020-01-23 09:02:29 -08:00
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common	Tegra: bpmp: fix header file paths	2020-01-23 08:58:17 -08:00
include	Tegra194: organize the memory/mmio map to make it linear	2020-01-23 09:02:12 -08:00
scat	spm: Remove SPM Alpha 1 prototype and support files	2019-12-20 16:03:32 +00:00
soc	Tegra194: access XUSB_PADCTL registers on Si/FPGA platforms	2020-01-23 09:02:29 -08:00
platform.mk	Tegra: dummy support for the io_storage backend	2019-03-01 10:22:54 -08:00