294 lines
12 KiB
C
294 lines
12 KiB
C
/*
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* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch_helpers.h>
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#include <assert.h>
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#include <bl_common.h>
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#include <bl2.h>
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#include <console.h>
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#include <platform.h>
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#include <string.h>
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/*******************************************************************************
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* Declarations of linker defined symbols which will help us find the layout
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* of trusted SRAM
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******************************************************************************/
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extern unsigned long __RO_START__;
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extern unsigned long __RO_END__;
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extern unsigned long __COHERENT_RAM_START__;
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extern unsigned long __COHERENT_RAM_END__;
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/*
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* The next 2 constants identify the extents of the code & RO data region.
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* These addresses are used by the MMU setup code and therefore they must be
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* page-aligned. It is the responsibility of the linker script to ensure that
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* __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses.
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*/
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#define BL2_RO_BASE (unsigned long)(&__RO_START__)
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#define BL2_RO_LIMIT (unsigned long)(&__RO_END__)
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/*
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* The next 2 constants identify the extents of the coherent memory region.
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* These addresses are used by the MMU setup code and therefore they must be
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* page-aligned. It is the responsibility of the linker script to ensure that
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* __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
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* page-aligned addresses.
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*/
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#define BL2_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
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#define BL2_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
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/* Pointer to memory visible to both BL2 and BL31 for passing data */
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extern unsigned char **bl2_el_change_mem_ptr;
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/* Data structure which holds the extents of the trusted SRAM for BL2 */
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static meminfo_t bl2_tzram_layout
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__attribute__ ((aligned(PLATFORM_CACHE_LINE_SIZE),
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section("tzfw_coherent_mem")));
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/*******************************************************************************
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* Reference to structures which holds the arguments which need to be passed
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* to BL31
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******************************************************************************/
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static bl31_params_t *bl2_to_bl31_params;
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static entry_point_info_t *bl31_ep_info;
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meminfo_t *bl2_plat_sec_mem_layout(void)
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{
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return &bl2_tzram_layout;
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}
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/*******************************************************************************
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* This function assigns a pointer to the memory that the platform has kept
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* aside to pass platform specific and trusted firmware related information
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* to BL31. This memory is allocated by allocating memory to
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* bl2_to_bl31_params_mem_t structure which is a superset of all the
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* structure whose information is passed to BL31
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* NOTE: This function should be called only once and should be done
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* before generating params to BL31
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******************************************************************************/
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bl31_params_t *bl2_plat_get_bl31_params(void)
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{
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bl2_to_bl31_params_mem_t *bl31_params_mem;
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/*
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* Ensure that the secure DRAM memory used for passing BL31 arguments
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* does not overlap with the BL32_BASE.
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*/
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assert(BL32_BASE > PARAMS_BASE + sizeof(bl2_to_bl31_params_mem_t));
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/*
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* Allocate the memory for all the arguments that needs to
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* be passed to BL31
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*/
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bl31_params_mem = (bl2_to_bl31_params_mem_t *)PARAMS_BASE;
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memset((void *)PARAMS_BASE, 0, sizeof(bl2_to_bl31_params_mem_t));
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/* Assign memory for TF related information */
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bl2_to_bl31_params = &bl31_params_mem->bl31_params;
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SET_PARAM_HEAD(bl2_to_bl31_params, PARAM_BL31, VERSION_1, 0);
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/* Fill BL31 related information */
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bl31_ep_info = &bl31_params_mem->bl31_ep_info;
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bl2_to_bl31_params->bl31_image_info = &bl31_params_mem->bl31_image_info;
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SET_PARAM_HEAD(bl2_to_bl31_params->bl31_image_info, PARAM_IMAGE_BINARY,
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VERSION_1, 0);
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/* Fill BL32 related information if it exists */
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if (BL32_BASE) {
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bl2_to_bl31_params->bl32_ep_info =
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&bl31_params_mem->bl32_ep_info;
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SET_PARAM_HEAD(bl2_to_bl31_params->bl32_ep_info,
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PARAM_EP, VERSION_1, 0);
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bl2_to_bl31_params->bl32_image_info =
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&bl31_params_mem->bl32_image_info;
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SET_PARAM_HEAD(bl2_to_bl31_params->bl32_image_info,
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PARAM_IMAGE_BINARY,
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VERSION_1, 0);
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}
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/* Fill BL33 related information */
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bl2_to_bl31_params->bl33_ep_info = &bl31_params_mem->bl33_ep_info;
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SET_PARAM_HEAD(bl2_to_bl31_params->bl33_ep_info,
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PARAM_EP, VERSION_1, 0);
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bl2_to_bl31_params->bl33_image_info = &bl31_params_mem->bl33_image_info;
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SET_PARAM_HEAD(bl2_to_bl31_params->bl33_image_info, PARAM_IMAGE_BINARY,
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VERSION_1, 0);
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return bl2_to_bl31_params;
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}
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/*******************************************************************************
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* This function returns a pointer to the shared memory that the platform
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* has kept to point to entry point information of BL31 to BL2
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******************************************************************************/
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struct entry_point_info *bl2_plat_get_bl31_ep_info(void)
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{
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return bl31_ep_info;
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}
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/*******************************************************************************
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* BL1 has passed the extents of the trusted SRAM that should be visible to BL2
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* in x0. This memory layout is sitting at the base of the free trusted SRAM.
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* Copy it to a safe loaction before its reclaimed by later BL2 functionality.
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******************************************************************************/
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void bl2_early_platform_setup(meminfo_t *mem_layout)
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{
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/* Initialize the console to provide early debug support */
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console_init(PL011_UART0_BASE);
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/* Setup the BL2 memory layout */
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bl2_tzram_layout.total_base = mem_layout->total_base;
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bl2_tzram_layout.total_size = mem_layout->total_size;
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bl2_tzram_layout.free_base = mem_layout->free_base;
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bl2_tzram_layout.free_size = mem_layout->free_size;
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bl2_tzram_layout.attr = mem_layout->attr;
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bl2_tzram_layout.next = 0;
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/* Initialize the platform config for future decision making */
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platform_config_setup();
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}
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/*******************************************************************************
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* Perform platform specific setup. For now just initialize the memory location
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* to use for passing arguments to BL31.
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******************************************************************************/
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void bl2_platform_setup(void)
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{
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/*
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* Do initial security configuration to allow DRAM/device access. On
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* Base FVP only DRAM security is programmable (via TrustZone), but
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* other platforms might have more programmable security devices
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* present.
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*/
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plat_security_setup();
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/* Initialise the IO layer and register platform IO devices */
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io_setup();
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}
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/* Flush the TF params and the TF plat params */
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void bl2_plat_flush_bl31_params(void)
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{
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flush_dcache_range((unsigned long)PARAMS_BASE, \
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sizeof(bl2_to_bl31_params_mem_t));
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}
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/*******************************************************************************
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* Perform the very early platform specific architectural setup here. At the
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* moment this is only intializes the mmu in a quick and dirty way.
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******************************************************************************/
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void bl2_plat_arch_setup()
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{
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configure_mmu_el1(bl2_tzram_layout.total_base,
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bl2_tzram_layout.total_size,
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BL2_RO_BASE,
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BL2_RO_LIMIT,
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BL2_COHERENT_RAM_BASE,
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BL2_COHERENT_RAM_LIMIT);
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}
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/*******************************************************************************
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* Before calling this function BL31 is loaded in memory and its entrypoint
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* is set by load_image. This is a placeholder for the platform to change
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* the entrypoint of BL31 and set SPSR and security state.
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* On FVP we are only setting the security state, entrypoint
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******************************************************************************/
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void bl2_plat_set_bl31_ep_info(image_info_t *bl31_image_info,
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entry_point_info_t *bl31_ep_info)
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{
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SET_SECURITY_STATE(bl31_ep_info->h.attr, SECURE);
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bl31_ep_info->spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
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DISABLE_ALL_EXCEPTIONS);
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}
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/*******************************************************************************
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* Before calling this function BL32 is loaded in memory and its entrypoint
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* is set by load_image. This is a placeholder for the platform to change
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* the entrypoint of BL32 and set SPSR and security state.
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* On FVP we are only setting the security state, entrypoint
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******************************************************************************/
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void bl2_plat_set_bl32_ep_info(image_info_t *bl32_image_info,
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entry_point_info_t *bl32_ep_info)
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{
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fvp_set_bl32_ep_info(bl32_ep_info);
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}
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/*******************************************************************************
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* Before calling this function BL33 is loaded in memory and its entrypoint
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* is set by load_image. This is a placeholder for the platform to change
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* the entrypoint of BL33 and set SPSR and security state.
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* On FVP we are only setting the security state, entrypoint
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******************************************************************************/
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void bl2_plat_set_bl33_ep_info(image_info_t *image,
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entry_point_info_t *bl33_ep_info)
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{
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fvp_set_bl33_ep_info(bl33_ep_info);
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}
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/*******************************************************************************
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* Populate the extents of memory available for loading BL32
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******************************************************************************/
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void bl2_plat_get_bl32_meminfo(meminfo_t *bl32_meminfo)
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{
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/*
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* Populate the extents of memory available for loading BL32.
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* TODO: We are temporarily executing BL2 from TZDRAM;
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* will eventually move to Trusted SRAM
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*/
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bl32_meminfo->total_base = BL32_BASE;
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bl32_meminfo->free_base = BL32_BASE;
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bl32_meminfo->total_size =
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(TZDRAM_BASE + TZDRAM_SIZE) - BL32_BASE;
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bl32_meminfo->free_size =
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(TZDRAM_BASE + TZDRAM_SIZE) - BL32_BASE;
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bl32_meminfo->attr = BOT_LOAD;
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bl32_meminfo->next = 0;
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}
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/*******************************************************************************
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* Populate the extents of memory available for loading BL33
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******************************************************************************/
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void bl2_plat_get_bl33_meminfo(meminfo_t *bl33_meminfo)
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{
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bl33_meminfo->total_base = DRAM_BASE;
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bl33_meminfo->total_size = DRAM_SIZE;
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bl33_meminfo->free_base = DRAM_BASE;
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bl33_meminfo->free_size = DRAM_SIZE;
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bl33_meminfo->attr = 0;
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bl33_meminfo->attr = 0;
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}
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