415 lines
15 KiB
C
415 lines
15 KiB
C
/*
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* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __GICV3_H__
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#define __GICV3_H__
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/*******************************************************************************
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* GICv3 miscellaneous definitions
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******************************************************************************/
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/* Interrupt group definitions */
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#define INTR_GROUP1S 0
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#define INTR_GROUP0 1
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#define INTR_GROUP1NS 2
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/* Interrupt IDs reported by the HPPIR and IAR registers */
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#define PENDING_G1S_INTID 1020
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#define PENDING_G1NS_INTID 1021
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/* Constant to categorize LPI interrupt */
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#define MIN_LPI_ID 8192
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/* GICv3 can only target up to 16 PEs with SGI */
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#define GICV3_MAX_SGI_TARGETS 16
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/*******************************************************************************
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* GICv3 specific Distributor interface register offsets and constants.
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******************************************************************************/
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#define GICD_STATUSR 0x10
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#define GICD_SETSPI_NSR 0x40
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#define GICD_CLRSPI_NSR 0x48
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#define GICD_SETSPI_SR 0x50
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#define GICD_CLRSPI_SR 0x50
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#define GICD_IGRPMODR 0xd00
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/*
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* GICD_IROUTER<n> register is at 0x6000 + 8n, where n is the interrupt id and
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* n >= 32, making the effective offset as 0x6100.
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*/
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#define GICD_IROUTER 0x6000
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#define GICD_PIDR2_GICV3 0xffe8
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#define IGRPMODR_SHIFT 5
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/* GICD_CTLR bit definitions */
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#define CTLR_ENABLE_G1NS_SHIFT 1
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#define CTLR_ENABLE_G1S_SHIFT 2
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#define CTLR_ARE_S_SHIFT 4
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#define CTLR_ARE_NS_SHIFT 5
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#define CTLR_DS_SHIFT 6
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#define CTLR_E1NWF_SHIFT 7
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#define GICD_CTLR_RWP_SHIFT 31
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#define CTLR_ENABLE_G1NS_MASK 0x1
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#define CTLR_ENABLE_G1S_MASK 0x1
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#define CTLR_ARE_S_MASK 0x1
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#define CTLR_ARE_NS_MASK 0x1
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#define CTLR_DS_MASK 0x1
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#define CTLR_E1NWF_MASK 0x1
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#define GICD_CTLR_RWP_MASK 0x1
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#define CTLR_ENABLE_G1NS_BIT (1 << CTLR_ENABLE_G1NS_SHIFT)
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#define CTLR_ENABLE_G1S_BIT (1 << CTLR_ENABLE_G1S_SHIFT)
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#define CTLR_ARE_S_BIT (1 << CTLR_ARE_S_SHIFT)
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#define CTLR_ARE_NS_BIT (1 << CTLR_ARE_NS_SHIFT)
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#define CTLR_DS_BIT (1 << CTLR_DS_SHIFT)
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#define CTLR_E1NWF_BIT (1 << CTLR_E1NWF_SHIFT)
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#define GICD_CTLR_RWP_BIT (1 << GICD_CTLR_RWP_SHIFT)
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/* GICD_IROUTER shifts and masks */
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#define IROUTER_SHIFT 0
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#define IROUTER_IRM_SHIFT 31
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#define IROUTER_IRM_MASK 0x1
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#define GICV3_IRM_PE 0
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#define GICV3_IRM_ANY 1
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#define NUM_OF_DIST_REGS 30
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/*******************************************************************************
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* GICv3 Re-distributor interface registers & constants
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******************************************************************************/
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#define GICR_PCPUBASE_SHIFT 0x11
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#define GICR_SGIBASE_OFFSET (1 << 0x10) /* 64 KB */
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#define GICR_CTLR 0x0
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#define GICR_TYPER 0x08
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#define GICR_WAKER 0x14
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#define GICR_PROPBASER 0x70
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#define GICR_PENDBASER 0x78
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#define GICR_IGROUPR0 (GICR_SGIBASE_OFFSET + 0x80)
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#define GICR_ISENABLER0 (GICR_SGIBASE_OFFSET + 0x100)
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#define GICR_ICENABLER0 (GICR_SGIBASE_OFFSET + 0x180)
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#define GICR_ISPENDR0 (GICR_SGIBASE_OFFSET + 0x200)
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#define GICR_ICPENDR0 (GICR_SGIBASE_OFFSET + 0x280)
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#define GICR_ISACTIVER0 (GICR_SGIBASE_OFFSET + 0x300)
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#define GICR_ICACTIVER0 (GICR_SGIBASE_OFFSET + 0x380)
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#define GICR_IPRIORITYR (GICR_SGIBASE_OFFSET + 0x400)
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#define GICR_ICFGR0 (GICR_SGIBASE_OFFSET + 0xc00)
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#define GICR_ICFGR1 (GICR_SGIBASE_OFFSET + 0xc04)
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#define GICR_IGRPMODR0 (GICR_SGIBASE_OFFSET + 0xd00)
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#define GICR_NSACR (GICR_SGIBASE_OFFSET + 0xe00)
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/* GICR_CTLR bit definitions */
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#define GICR_CTLR_UWP_SHIFT 31
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#define GICR_CTLR_UWP_MASK 0x1
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#define GICR_CTLR_UWP_BIT (1U << GICR_CTLR_UWP_SHIFT)
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#define GICR_CTLR_RWP_SHIFT 3
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#define GICR_CTLR_RWP_MASK 0x1
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#define GICR_CTLR_RWP_BIT (1U << GICR_CTLR_RWP_SHIFT)
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#define GICR_CTLR_EN_LPIS_BIT (1U << 0)
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/* GICR_WAKER bit definitions */
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#define WAKER_CA_SHIFT 2
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#define WAKER_PS_SHIFT 1
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#define WAKER_CA_MASK 0x1
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#define WAKER_PS_MASK 0x1
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#define WAKER_CA_BIT (1 << WAKER_CA_SHIFT)
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#define WAKER_PS_BIT (1 << WAKER_PS_SHIFT)
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/* GICR_TYPER bit definitions */
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#define TYPER_AFF_VAL_SHIFT 32
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#define TYPER_PROC_NUM_SHIFT 8
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#define TYPER_LAST_SHIFT 4
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#define TYPER_AFF_VAL_MASK 0xffffffff
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#define TYPER_PROC_NUM_MASK 0xffff
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#define TYPER_LAST_MASK 0x1
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#define TYPER_LAST_BIT (1 << TYPER_LAST_SHIFT)
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#define NUM_OF_REDIST_REGS 30
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/*******************************************************************************
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* GICv3 CPU interface registers & constants
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******************************************************************************/
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/* ICC_SRE bit definitions*/
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#define ICC_SRE_EN_BIT (1 << 3)
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#define ICC_SRE_DIB_BIT (1 << 2)
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#define ICC_SRE_DFB_BIT (1 << 1)
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#define ICC_SRE_SRE_BIT (1 << 0)
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/* ICC_IGRPEN1_EL3 bit definitions */
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#define IGRPEN1_EL3_ENABLE_G1NS_SHIFT 0
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#define IGRPEN1_EL3_ENABLE_G1S_SHIFT 1
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#define IGRPEN1_EL3_ENABLE_G1NS_BIT (1 << IGRPEN1_EL3_ENABLE_G1NS_SHIFT)
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#define IGRPEN1_EL3_ENABLE_G1S_BIT (1 << IGRPEN1_EL3_ENABLE_G1S_SHIFT)
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/* ICC_IGRPEN0_EL1 bit definitions */
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#define IGRPEN1_EL1_ENABLE_G0_SHIFT 0
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#define IGRPEN1_EL1_ENABLE_G0_BIT (1 << IGRPEN1_EL1_ENABLE_G0_SHIFT)
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/* ICC_HPPIR0_EL1 bit definitions */
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#define HPPIR0_EL1_INTID_SHIFT 0
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#define HPPIR0_EL1_INTID_MASK 0xffffff
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/* ICC_HPPIR1_EL1 bit definitions */
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#define HPPIR1_EL1_INTID_SHIFT 0
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#define HPPIR1_EL1_INTID_MASK 0xffffff
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/* ICC_IAR0_EL1 bit definitions */
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#define IAR0_EL1_INTID_SHIFT 0
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#define IAR0_EL1_INTID_MASK 0xffffff
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/* ICC_IAR1_EL1 bit definitions */
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#define IAR1_EL1_INTID_SHIFT 0
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#define IAR1_EL1_INTID_MASK 0xffffff
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/* ICC SGI macros */
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#define SGIR_TGT_MASK 0xffff
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#define SGIR_AFF1_SHIFT 16
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#define SGIR_INTID_SHIFT 24
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#define SGIR_INTID_MASK 0xf
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#define SGIR_AFF2_SHIFT 32
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#define SGIR_IRM_SHIFT 40
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#define SGIR_IRM_MASK 0x1
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#define SGIR_AFF3_SHIFT 48
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#define SGIR_AFF_MASK 0xf
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#define SGIR_IRM_TO_AFF 0
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#define GICV3_SGIR_VALUE(aff3, aff2, aff1, intid, irm, tgt) \
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((((uint64_t) (aff3) & SGIR_AFF_MASK) << SGIR_AFF3_SHIFT) | \
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(((uint64_t) (irm) & SGIR_IRM_MASK) << SGIR_IRM_SHIFT) | \
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(((uint64_t) (aff2) & SGIR_AFF_MASK) << SGIR_AFF2_SHIFT) | \
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(((intid) & SGIR_INTID_MASK) << SGIR_INTID_SHIFT) | \
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(((aff1) & SGIR_AFF_MASK) << SGIR_AFF1_SHIFT) | \
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((tgt) & SGIR_TGT_MASK))
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/*****************************************************************************
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* GICv3 ITS registers and constants
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*****************************************************************************/
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#define GITS_CTLR 0x0
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#define GITS_IIDR 0x4
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#define GITS_TYPER 0x8
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#define GITS_CBASER 0x80
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#define GITS_CWRITER 0x88
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#define GITS_CREADR 0x90
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#define GITS_BASER 0x100
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/* GITS_CTLR bit definitions */
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#define GITS_CTLR_ENABLED_BIT 1
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#define GITS_CTLR_QUIESCENT_SHIFT 31
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#define GITS_CTLR_QUIESCENT_BIT (1U << GITS_CTLR_QUIESCENT_SHIFT)
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#ifndef __ASSEMBLY__
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#include <gic_common.h>
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#include <interrupt_props.h>
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#include <stdint.h>
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#include <types.h>
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#include <utils_def.h>
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#define gicv3_is_intr_id_special_identifier(id) \
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(((id) >= PENDING_G1S_INTID) && ((id) <= GIC_SPURIOUS_INTERRUPT))
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/*******************************************************************************
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* Helper GICv3 macros for SEL1
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******************************************************************************/
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#define gicv3_acknowledge_interrupt_sel1() read_icc_iar1_el1() &\
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IAR1_EL1_INTID_MASK
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#define gicv3_get_pending_interrupt_id_sel1() read_icc_hppir1_el1() &\
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HPPIR1_EL1_INTID_MASK
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#define gicv3_end_of_interrupt_sel1(id) write_icc_eoir1_el1(id)
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/*******************************************************************************
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* Helper GICv3 macros for EL3
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******************************************************************************/
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#define gicv3_acknowledge_interrupt() read_icc_iar0_el1() &\
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IAR0_EL1_INTID_MASK
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#define gicv3_end_of_interrupt(id) write_icc_eoir0_el1(id)
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/*
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* This macro returns the total number of GICD registers corresponding to
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* the name.
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*/
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#define GICD_NUM_REGS(reg_name) \
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DIV_ROUND_UP_2EVAL(TOTAL_SPI_INTR_NUM, (1 << reg_name ## _SHIFT))
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#define GICR_NUM_REGS(reg_name) \
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DIV_ROUND_UP_2EVAL(TOTAL_PCPU_INTR_NUM, (1 << reg_name ## _SHIFT))
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/* Interrupt ID mask for HPPIR, AHPPIR, IAR and AIAR CPU Interface registers */
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#define INT_ID_MASK 0xffffff
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/*******************************************************************************
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* This structure describes some of the implementation defined attributes of the
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* GICv3 IP. It is used by the platform port to specify these attributes in order
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* to initialise the GICV3 driver. The attributes are described below.
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*
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* The 'gicd_base' field contains the base address of the Distributor interface
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* programmer's view.
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*
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* The 'gicr_base' field contains the base address of the Re-distributor
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* interface programmer's view.
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*
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* The 'g0_interrupt_array' field is a pointer to an array in which each entry
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* corresponds to an ID of a Group 0 interrupt. This field is ignored when
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* 'interrupt_props' field is used. This field is deprecated.
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*
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* The 'g0_interrupt_num' field contains the number of entries in the
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* 'g0_interrupt_array'. This field is ignored when 'interrupt_props' field is
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* used. This field is deprecated.
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*
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* The 'g1s_interrupt_array' field is a pointer to an array in which each entry
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* corresponds to an ID of a Group 1 interrupt. This field is ignored when
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* 'interrupt_props' field is used. This field is deprecated.
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*
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* The 'g1s_interrupt_num' field contains the number of entries in the
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* 'g1s_interrupt_array'. This field must be 0 if 'interrupt_props' field is
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* used. This field is ignored when 'interrupt_props' field is used. This field
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* is deprecated.
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*
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* The 'interrupt_props' field is a pointer to an array that enumerates secure
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* interrupts and their properties. If this field is not NULL, both
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* 'g0_interrupt_array' and 'g1s_interrupt_array' fields are ignored.
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*
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* The 'interrupt_props_num' field contains the number of entries in the
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* 'interrupt_props' array. If this field is non-zero, both 'g0_interrupt_num'
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* and 'g1s_interrupt_num' are ignored.
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*
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* The 'rdistif_num' field contains the number of Redistributor interfaces the
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* GIC implements. This is equal to the number of CPUs or CPU interfaces
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* instantiated in the GIC.
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*
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* The 'rdistif_base_addrs' field is a pointer to an array that has an entry for
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* storing the base address of the Redistributor interface frame of each CPU in
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* the system. The size of the array = 'rdistif_num'. The base addresses are
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* detected during driver initialisation.
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*
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* The 'mpidr_to_core_pos' field is a pointer to a hash function which the
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* driver will use to convert an MPIDR value to a linear core index. This index
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* will be used for accessing the 'rdistif_base_addrs' array. This is an
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* optional field. A GICv3 implementation maps each MPIDR to a linear core index
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* as well. This mapping can be found by reading the "Affinity Value" and
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* "Processor Number" fields in the GICR_TYPER. It is IMP. DEF. if the
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* "Processor Numbers" are suitable to index into an array to access core
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* specific information. If this not the case, the platform port must provide a
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* hash function. Otherwise, the "Processor Number" field will be used to access
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* the array elements.
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******************************************************************************/
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typedef unsigned int (*mpidr_hash_fn)(u_register_t mpidr);
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typedef struct gicv3_driver_data {
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uintptr_t gicd_base;
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uintptr_t gicr_base;
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#if !ERROR_DEPRECATED
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unsigned int g0_interrupt_num __deprecated;
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unsigned int g1s_interrupt_num __deprecated;
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const unsigned int *g0_interrupt_array __deprecated;
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const unsigned int *g1s_interrupt_array __deprecated;
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#endif
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const interrupt_prop_t *interrupt_props;
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unsigned int interrupt_props_num;
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unsigned int rdistif_num;
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uintptr_t *rdistif_base_addrs;
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mpidr_hash_fn mpidr_to_core_pos;
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} gicv3_driver_data_t;
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typedef struct gicv3_redist_ctx {
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/* 64 bits registers */
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uint64_t gicr_propbaser;
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uint64_t gicr_pendbaser;
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/* 32 bits registers */
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uint32_t gicr_ctlr;
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uint32_t gicr_igroupr0;
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uint32_t gicr_isenabler0;
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uint32_t gicr_ispendr0;
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uint32_t gicr_isactiver0;
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uint32_t gicr_ipriorityr[GICR_NUM_REGS(IPRIORITYR)];
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uint32_t gicr_icfgr0;
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uint32_t gicr_icfgr1;
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uint32_t gicr_igrpmodr0;
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uint32_t gicr_nsacr;
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} gicv3_redist_ctx_t;
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typedef struct gicv3_dist_ctx {
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/* 64 bits registers */
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uint64_t gicd_irouter[TOTAL_SPI_INTR_NUM];
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/* 32 bits registers */
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uint32_t gicd_ctlr;
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uint32_t gicd_igroupr[GICD_NUM_REGS(IGROUPR)];
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uint32_t gicd_isenabler[GICD_NUM_REGS(ISENABLER)];
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uint32_t gicd_ispendr[GICD_NUM_REGS(ISPENDR)];
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uint32_t gicd_isactiver[GICD_NUM_REGS(ISACTIVER)];
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uint32_t gicd_ipriorityr[GICD_NUM_REGS(IPRIORITYR)];
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uint32_t gicd_icfgr[GICD_NUM_REGS(ICFGR)];
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uint32_t gicd_igrpmodr[GICD_NUM_REGS(IGRPMODR)];
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uint32_t gicd_nsacr[GICD_NUM_REGS(NSACR)];
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} gicv3_dist_ctx_t;
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typedef struct gicv3_its_ctx {
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/* 64 bits registers */
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uint64_t gits_cbaser;
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uint64_t gits_cwriter;
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uint64_t gits_baser[8];
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/* 32 bits registers */
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uint32_t gits_ctlr;
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} gicv3_its_ctx_t;
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/*******************************************************************************
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* GICv3 EL3 driver API
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******************************************************************************/
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void gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data);
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void gicv3_distif_init(void);
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void gicv3_rdistif_init(unsigned int proc_num);
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void gicv3_rdistif_on(unsigned int proc_num);
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void gicv3_rdistif_off(unsigned int proc_num);
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void gicv3_cpuif_enable(unsigned int proc_num);
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void gicv3_cpuif_disable(unsigned int proc_num);
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unsigned int gicv3_get_pending_interrupt_type(void);
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unsigned int gicv3_get_pending_interrupt_id(void);
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unsigned int gicv3_get_interrupt_type(unsigned int id,
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unsigned int proc_num);
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void gicv3_distif_init_restore(const gicv3_dist_ctx_t * const dist_ctx);
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void gicv3_distif_save(gicv3_dist_ctx_t * const dist_ctx);
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/*
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* gicv3_distif_post_restore and gicv3_distif_pre_save must be implemented if
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* gicv3_distif_save and gicv3_rdistif_init_restore are used. If no
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* implementation-defined sequence is needed at these steps, an empty function
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* can be provided.
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*/
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void gicv3_distif_post_restore(unsigned int proc_num);
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void gicv3_distif_pre_save(unsigned int proc_num);
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void gicv3_rdistif_init_restore(unsigned int proc_num, const gicv3_redist_ctx_t * const rdist_ctx);
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void gicv3_rdistif_save(unsigned int proc_num, gicv3_redist_ctx_t * const rdist_ctx);
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void gicv3_its_save_disable(uintptr_t gits_base, gicv3_its_ctx_t * const its_ctx);
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void gicv3_its_restore(uintptr_t gits_base, const gicv3_its_ctx_t * const its_ctx);
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unsigned int gicv3_get_running_priority(void);
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unsigned int gicv3_get_interrupt_active(unsigned int id, unsigned int proc_num);
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void gicv3_enable_interrupt(unsigned int id, unsigned int proc_num);
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void gicv3_disable_interrupt(unsigned int id, unsigned int proc_num);
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void gicv3_set_interrupt_priority(unsigned int id, unsigned int proc_num,
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unsigned int priority);
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void gicv3_set_interrupt_type(unsigned int id, unsigned int proc_num,
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unsigned int type);
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void gicv3_raise_secure_g0_sgi(int sgi_num, u_register_t target);
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void gicv3_set_spi_routing(unsigned int id, unsigned int irm,
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u_register_t mpidr);
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void gicv3_set_interrupt_pending(unsigned int id, unsigned int proc_num);
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void gicv3_clear_interrupt_pending(unsigned int id, unsigned int proc_num);
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unsigned int gicv3_set_pmr(unsigned int mask);
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#endif /* __ASSEMBLY__ */
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#endif /* __GICV3_H__ */
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