44 lines
1.3 KiB
C
44 lines
1.3 KiB
C
/*
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* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef BOARD_DEF_H
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#define BOARD_DEF_H
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#include <lib/utils_def.h>
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/* The ports must be in order and contiguous */
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#define K3_CLUSTER0_CORE_COUNT U(2)
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#define K3_CLUSTER1_CORE_COUNT U(2)
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#define K3_CLUSTER2_CORE_COUNT U(2)
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#define K3_CLUSTER3_CORE_COUNT U(2)
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/*
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* This RAM will be used for the bootloader including code, bss, and stacks.
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* It may need to be increased if BL31 grows in size.
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*
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* The link addresses are determined by SEC_SRAM_BASE + offset.
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* When ENABLE_PIE is set, the TF images can be loaded anywhere, so
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* SEC_SRAM_BASE is really arbitrary.
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*
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* When ENABLE_PIE is unset, SEC_SRAM_BASE should be chosen so that
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* it matches to the physical address where BL31 is loaded, that is,
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* SEC_SRAM_BASE should be the base address of the RAM region.
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*
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* Lets make things explicit by mapping SRAM_BASE to 0x0 since ENABLE_PIE is
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* defined as default for our platform.
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*/
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#define SEC_SRAM_BASE UL(0x00000000) /* PIE remapped on fly */
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#define SEC_SRAM_SIZE UL(0x00020000) /* 128k */
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#define PLAT_MAX_OFF_STATE U(2)
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#define PLAT_MAX_RET_STATE U(1)
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#define PLAT_PROC_START_ID U(32)
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#define PLAT_PROC_DEVICE_START_ID U(202)
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#define PLAT_CLUSTER_DEVICE_START_ID U(198)
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#endif /* BOARD_DEF_H */
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