214 lines
8.2 KiB
C
214 lines
8.2 KiB
C
/*
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* Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __PLATFORM_DEF_H__
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#define __PLATFORM_DEF_H__
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#include <arch.h>
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#include "../juno_def.h"
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/*******************************************************************************
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* Platform binary types for linking
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******************************************************************************/
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#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
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#define PLATFORM_LINKER_ARCH aarch64
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/*******************************************************************************
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* Generic platform constants
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******************************************************************************/
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/* Size of cacheable stacks */
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#if TRUSTED_BOARD_BOOT && (IMAGE_BL1 || IMAGE_BL2)
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#define PLATFORM_STACK_SIZE 0x1000
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#else
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#define PLATFORM_STACK_SIZE 0x800
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#endif
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#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n"
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/* Trusted Boot Firmware BL2 */
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#define BL2_IMAGE_NAME "bl2.bin"
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/* EL3 Runtime Firmware BL3-1 */
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#define BL31_IMAGE_NAME "bl31.bin"
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/* SCP Firmware BL3-0 */
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#define BL30_IMAGE_NAME "bl30.bin"
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/* Secure Payload BL3-2 (Trusted OS) */
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#define BL32_IMAGE_NAME "bl32.bin"
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/* Non-Trusted Firmware BL3-3 */
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#define BL33_IMAGE_NAME "bl33.bin" /* e.g. UEFI */
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/* Firmware Image Package */
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#define FIP_IMAGE_NAME "fip.bin"
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#if TRUSTED_BOARD_BOOT
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/* Certificates */
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# define BL2_CERT_NAME "bl2.crt"
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# define TRUSTED_KEY_CERT_NAME "trusted_key.crt"
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# define BL30_KEY_CERT_NAME "bl30_key.crt"
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# define BL31_KEY_CERT_NAME "bl31_key.crt"
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# define BL32_KEY_CERT_NAME "bl32_key.crt"
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# define BL33_KEY_CERT_NAME "bl33_key.crt"
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# define BL30_CERT_NAME "bl30.crt"
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# define BL31_CERT_NAME "bl31.crt"
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# define BL32_CERT_NAME "bl32.crt"
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# define BL33_CERT_NAME "bl33.crt"
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#endif /* TRUSTED_BOARD_BOOT */
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#define PLATFORM_CACHE_LINE_SIZE 64
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#define PLATFORM_CLUSTER_COUNT 2
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#define PLATFORM_CORE_COUNT 6
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#define PLATFORM_NUM_AFFS (PLATFORM_CLUSTER_COUNT + \
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PLATFORM_CORE_COUNT)
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#define MAX_IO_DEVICES 3
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#define MAX_IO_HANDLES 4
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/*******************************************************************************
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* BL1 specific defines.
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* BL1 RW data is relocated from ROM to RAM at runtime so we need 2 base
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* addresses.
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******************************************************************************/
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#define BL1_RO_BASE TZROM_BASE
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#define BL1_RO_LIMIT (TZROM_BASE + TZROM_SIZE)
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/*
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* Put BL1 RW at the top of the Trusted SRAM. BL1_RW_BASE is calculated using
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* the current BL1 RW debug size plus a little space for growth.
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*/
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#if TRUSTED_BOARD_BOOT
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#define BL1_RW_BASE (TZRAM_BASE + TZRAM_SIZE - 0x8000)
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#else
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#define BL1_RW_BASE (TZRAM_BASE + TZRAM_SIZE - 0x6000)
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#endif
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#define BL1_RW_LIMIT (TZRAM_BASE + TZRAM_SIZE)
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/*******************************************************************************
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* BL2 specific defines.
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******************************************************************************/
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/*
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* Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug
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* size plus a little space for growth.
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*/
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#if TRUSTED_BOARD_BOOT
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#define BL2_BASE (BL31_BASE - 0x1D000)
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#else
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#define BL2_BASE (BL31_BASE - 0xC000)
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#endif
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#define BL2_LIMIT BL31_BASE
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/*******************************************************************************
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* Load address of BL3-0 in the Juno port
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* BL3-0 is loaded to the same place as BL3-1. Once BL3-0 is transferred to the
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* SCP, it is discarded and BL3-1 is loaded over the top.
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******************************************************************************/
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#define BL30_BASE BL31_BASE
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/*******************************************************************************
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* BL3-1 specific defines.
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******************************************************************************/
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/*
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* Put BL3-1 at the top of the Trusted SRAM. BL31_BASE is calculated using the
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* current BL3-1 debug size plus a little space for growth.
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*/
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#define BL31_BASE (TZRAM_BASE + TZRAM_SIZE - 0x1D000)
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#define BL31_PROGBITS_LIMIT BL1_RW_BASE
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#define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE)
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/*******************************************************************************
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* BL3-2 specific defines.
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******************************************************************************/
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#if (PLAT_TSP_LOCATION_ID == PLAT_TRUSTED_SRAM_ID)
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# define TSP_SEC_MEM_BASE TZRAM_BASE
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# define TSP_SEC_MEM_SIZE TZRAM_SIZE
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# define BL32_BASE TZRAM_BASE
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# define BL32_LIMIT BL31_BASE
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# define BL32_PROGBITS_LIMIT BL2_BASE
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#elif (PLAT_TSP_LOCATION_ID == PLAT_DRAM_ID)
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# define TSP_SEC_MEM_BASE DRAM_SEC_BASE
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# define TSP_SEC_MEM_SIZE (DRAM_SEC_SIZE - DRAM_SCP_SIZE)
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# define BL32_BASE DRAM_SEC_BASE
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# define BL32_LIMIT (DRAM_SEC_BASE + DRAM_SEC_SIZE - \
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DRAM_SCP_SIZE)
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#else
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# error "Unsupported PLAT_TSP_LOCATION_ID value"
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#endif
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/*******************************************************************************
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* Load address of BL3-3 in the Juno port
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******************************************************************************/
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#define NS_IMAGE_OFFSET 0xE0000000
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/*******************************************************************************
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* Platform specific page table and MMU setup constants
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******************************************************************************/
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#define ADDR_SPACE_SIZE (1ull << 32)
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#if IMAGE_BL1 || IMAGE_BL31
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# define MAX_XLAT_TABLES 2
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#endif
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#if IMAGE_BL2 || IMAGE_BL32
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# define MAX_XLAT_TABLES 3
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#endif
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#define MAX_MMAP_REGIONS 16
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/*******************************************************************************
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* ID of the secure physical generic timer interrupt used by the TSP
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******************************************************************************/
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#define TSP_IRQ_SEC_PHY_TIMER IRQ_SEC_PHY_TIMER
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/*******************************************************************************
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* Declarations and constants to access the mailboxes safely. Each mailbox is
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* aligned on the biggest cache line size in the platform. This is known only
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* to the platform as it might have a combination of integrated and external
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* caches. Such alignment ensures that two maiboxes do not sit on the same cache
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* line at any cache level. They could belong to different cpus/clusters &
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* get written while being protected by different locks causing corruption of
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* a valid mailbox address.
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******************************************************************************/
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#define CACHE_WRITEBACK_SHIFT 6
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#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
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#if !USE_COHERENT_MEM
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/*******************************************************************************
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* Size of the per-cpu data in bytes that should be reserved in the generic
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* per-cpu data structure for the Juno port.
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******************************************************************************/
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#define PLAT_PCPU_DATA_SIZE 2
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#endif
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#endif /* __PLATFORM_DEF_H__ */
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