157 lines
3.5 KiB
C
157 lines
3.5 KiB
C
/*
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* Copyright 2020-2022 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#include <common/debug.h>
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#include "dcfg.h"
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#include <lib/mmio.h>
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#ifdef NXP_SFP_ENABLED
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#include <sfp.h>
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#endif
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static soc_info_t soc_info = {0};
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static devdisr5_info_t devdisr5_info = {0};
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static dcfg_init_info_t *dcfg_init_info;
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/* Read the PORSR1 register */
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uint32_t read_reg_porsr1(void)
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{
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unsigned int *porsr1_addr = NULL;
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if (dcfg_init_info->porsr1 != 0U) {
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return dcfg_init_info->porsr1;
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}
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porsr1_addr = (void *)
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(dcfg_init_info->g_nxp_dcfg_addr + DCFG_PORSR1_OFFSET);
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dcfg_init_info->porsr1 = gur_in32(porsr1_addr);
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return dcfg_init_info->porsr1;
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}
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const soc_info_t *get_soc_info(void)
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{
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uint32_t reg;
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if (soc_info.is_populated == true) {
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return (const soc_info_t *) &soc_info;
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}
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reg = gur_in32(dcfg_init_info->g_nxp_dcfg_addr + DCFG_SVR_OFFSET);
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soc_info.svr_reg.val = reg;
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/* zero means SEC enabled. */
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soc_info.sec_enabled =
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(((reg & SVR_SEC_MASK) >> SVR_SEC_SHIFT) == 0) ? true : false;
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soc_info.is_populated = true;
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return (const soc_info_t *) &soc_info;
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}
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void dcfg_init(dcfg_init_info_t *dcfg_init_data)
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{
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dcfg_init_info = dcfg_init_data;
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read_reg_porsr1();
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get_soc_info();
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}
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bool is_sec_enabled(void)
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{
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return soc_info.sec_enabled;
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}
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const devdisr5_info_t *get_devdisr5_info(void)
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{
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uint32_t reg;
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if (devdisr5_info.is_populated == true)
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return (const devdisr5_info_t *) &devdisr5_info;
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reg = gur_in32(dcfg_init_info->g_nxp_dcfg_addr + DCFG_DEVDISR5_OFFSET);
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devdisr5_info.ddrc1_present = (reg & DISR5_DDRC1_MASK) ? 0 : 1;
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#if defined(CONFIG_CHASSIS_3_2)
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devdisr5_info.ddrc2_present = (reg & DISR5_DDRC2_MASK) ? 0 : 1;
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#endif
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devdisr5_info.ocram_present = (reg & DISR5_OCRAM_MASK) ? 0 : 1;
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devdisr5_info.is_populated = true;
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return (const devdisr5_info_t *) &devdisr5_info;
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}
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int get_clocks(struct sysinfo *sys)
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{
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unsigned int *rcwsr0 = NULL;
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const unsigned long sysclk = dcfg_init_info->nxp_sysclk_freq;
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const unsigned long ddrclk = dcfg_init_info->nxp_ddrclk_freq;
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rcwsr0 = (void *)(dcfg_init_info->g_nxp_dcfg_addr + RCWSR0_OFFSET);
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sys->freq_platform = sysclk;
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sys->freq_ddr_pll0 = ddrclk;
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sys->freq_ddr_pll1 = ddrclk;
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sys->freq_platform *= (gur_in32(rcwsr0) >>
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RCWSR0_SYS_PLL_RAT_SHIFT) &
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RCWSR0_SYS_PLL_RAT_MASK;
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sys->freq_platform /= dcfg_init_info->nxp_plat_clk_divider;
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sys->freq_ddr_pll0 *= (gur_in32(rcwsr0) >>
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RCWSR0_MEM_PLL_RAT_SHIFT) &
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RCWSR0_MEM_PLL_RAT_MASK;
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sys->freq_ddr_pll1 *= (gur_in32(rcwsr0) >>
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RCWSR0_MEM2_PLL_RAT_SHIFT) &
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RCWSR0_MEM2_PLL_RAT_MASK;
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if (sys->freq_platform == 0) {
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return 1;
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} else {
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return 0;
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}
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}
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#ifdef NXP_SFP_ENABLED
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/*******************************************************************************
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* Returns true if secur eboot is enabled on board
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* mode = 0 (development mode - sb_en = 1)
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* mode = 1 (production mode - ITS = 1)
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******************************************************************************/
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bool check_boot_mode_secure(uint32_t *mode)
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{
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uint32_t val = 0U;
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uint32_t *rcwsr = NULL;
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*mode = 0U;
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if (sfp_check_its() == 1) {
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/* ITS =1 , Production mode */
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*mode = 1U;
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return true;
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}
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rcwsr = (void *)(dcfg_init_info->g_nxp_dcfg_addr + RCWSR_SB_EN_OFFSET);
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val = (gur_in32(rcwsr) >> RCWSR_SBEN_SHIFT) &
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RCWSR_SBEN_MASK;
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if (val == RCWSR_SBEN_MASK) {
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*mode = 0U;
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return true;
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}
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return false;
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}
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#endif
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void error_handler(int error_code)
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{
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/* Dump error code in SCRATCH4 register */
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INFO("Error in Fuse Provisioning: %x\n", error_code);
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gur_out32((void *)
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(dcfg_init_info->g_nxp_dcfg_addr + DCFG_SCRATCH4_OFFSET),
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error_code);
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}
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