30 lines
1.1 KiB
C
30 lines
1.1 KiB
C
/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __CORTEX_HELIOS_H__
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#define __CORTEX_HELIOS_H__
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#define CORTEX_HELIOS_MIDR U(0x410FD060)
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/*******************************************************************************
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* CPU Extended Control register specific definitions.
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******************************************************************************/
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#define CORTEX_HELIOS_ECTLR_EL1 S3_0_C15_C1_4
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/*******************************************************************************
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* CPU Auxiliary Control register specific definitions.
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******************************************************************************/
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#define CORTEX_HELIOS_CPUACTLR_EL1 S3_0_C15_C1_0
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/*******************************************************************************
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* CPU Power Control register specific definitions.
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******************************************************************************/
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#define CORTEX_HELIOS_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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#define CORTEX_HELIOS_CPUPWRCTLR_EL1_CORE_PWRDN_BIT (U(1) << 0)
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#endif /* __CORTEX_HELIOS_H__ */
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