Dimitris Papastamos d6b798097e Implement dynamic mitigation for CVE-2018-3639 on Cortex-A76 ... The Cortex-A76 implements SMCCC_ARCH_WORKAROUND_2 as defined in "Firmware interfaces for mitigating cache speculation vulnerabilities System Software on Arm Systems"[0]. Dynamic mitigation for CVE-2018-3639 is enabled/disabled by setting/clearning bit 16 (Disable load pass store) of `CPUACTLR2_EL1`. NOTE: The generic code that implements dynamic mitigation does not currently implement the expected semantics when dispatching an SDEI event to a lower EL. This will be fixed in a separate patch. [0] https://developer.arm.com/cache-speculation-vulnerability-firmware-specification Change-Id: I8fb2862b9ab24d55a0e9693e48e8be4df32afb5a Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>		2018-06-08 11:46:31 +01:00
..
aem_generic.h	Use SPDX license identifiers	2017-05-03 09:39:28 +01:00
cortex_a35.h	Use SPDX license identifiers	2017-05-03 09:39:28 +01:00
cortex_a53.h	CPU: Correct names of implementation-defined aux regs	2017-08-29 13:52:48 +01:00
cortex_a55.h	Add support for Cortex-A75 and Cortex-A55 CPUs	2017-06-01 11:44:52 +01:00
cortex_a57.h	Implement static workaround for CVE-2018-3639	2018-05-23 12:45:48 +01:00
cortex_a72.h	Implement static workaround for CVE-2018-3639	2018-05-23 12:45:48 +01:00
cortex_a73.h	Implement static workaround for CVE-2018-3639	2018-05-23 12:45:48 +01:00
cortex_a75.h	Implement static workaround for CVE-2018-3639	2018-05-23 12:45:48 +01:00
cortex_a76.h	Implement dynamic mitigation for CVE-2018-3639 on Cortex-A76	2018-06-08 11:46:31 +01:00
cortex_ares.h	Implement Cortex-Ares 1043202 erratum workaround	2018-06-08 11:46:31 +01:00
cpu_macros.S	Add support for dynamic mitigation for CVE-2018-3639	2018-05-23 12:45:48 +01:00
cpuamu.h	Refactor AMU support for Cortex A75	2018-02-27 13:28:41 +00:00
denver.h	include: add U()/ULL() macros for constants	2017-06-14 17:00:30 -07:00