108 lines
3.0 KiB
C
108 lines
3.0 KiB
C
/*
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* Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef MEMCTRL_V2_H
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#define MEMCTRL_V2_H
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#include <arch.h>
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#include <tegra_def.h>
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/*******************************************************************************
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* Memory Controller SMMU Bypass config register
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******************************************************************************/
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#define MC_SMMU_BYPASS_CONFIG 0x1820U
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#define MC_SMMU_BYPASS_CTRL_MASK 0x3U
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#define MC_SMMU_BYPASS_CTRL_SHIFT 0U
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#define MC_SMMU_CTRL_TBU_BYPASS_ALL (0U << MC_SMMU_BYPASS_CTRL_SHIFT)
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#define MC_SMMU_CTRL_TBU_RSVD (1U << MC_SMMU_BYPASS_CTRL_SHIFT)
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#define MC_SMMU_CTRL_TBU_BYPASS_SPL_STREAMID (2U << MC_SMMU_BYPASS_CTRL_SHIFT)
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#define MC_SMMU_CTRL_TBU_BYPASS_NONE (3U << MC_SMMU_BYPASS_CTRL_SHIFT)
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#define MC_SMMU_BYPASS_CONFIG_WRITE_ACCESS_BIT (1U << 31)
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#define MC_SMMU_BYPASS_CONFIG_SETTINGS (MC_SMMU_BYPASS_CONFIG_WRITE_ACCESS_BIT | \
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MC_SMMU_CTRL_TBU_BYPASS_SPL_STREAMID)
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#ifndef __ASSEMBLER__
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#include <assert.h>
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typedef struct mc_regs {
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uint32_t reg;
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uint32_t val;
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} mc_regs_t;
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#define mc_smmu_bypass_cfg \
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{ \
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.reg = TEGRA_MC_BASE + MC_SMMU_BYPASS_CONFIG, \
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.val = 0x00000000U, \
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}
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#define _START_OF_TABLE_ \
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{ \
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.reg = 0xCAFE05C7U, \
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.val = 0x00000000U, \
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}
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#define _END_OF_TABLE_ \
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{ \
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.reg = 0xFFFFFFFFU, \
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.val = 0xFFFFFFFFU, \
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}
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#endif /* __ASSEMBLER__ */
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#ifndef __ASSEMBLER__
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#include <lib/mmio.h>
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static inline uint32_t tegra_mc_read_32(uint32_t off)
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{
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return mmio_read_32(TEGRA_MC_BASE + off);
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}
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static inline void tegra_mc_write_32(uint32_t off, uint32_t val)
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{
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mmio_write_32(TEGRA_MC_BASE + off, val);
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}
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#if defined(TEGRA_MC_STREAMID_BASE)
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static inline uint32_t tegra_mc_streamid_read_32(uint32_t off)
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{
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return mmio_read_32(TEGRA_MC_STREAMID_BASE + off);
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}
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static inline void tegra_mc_streamid_write_32(uint32_t off, uint32_t val)
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{
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mmio_write_32(TEGRA_MC_STREAMID_BASE + off, val);
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assert(mmio_read_32(TEGRA_MC_STREAMID_BASE + off) == val);
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}
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#endif
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void plat_memctrl_setup(void);
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void plat_memctrl_restore(void);
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mc_regs_t *plat_memctrl_get_sys_suspend_ctx(void);
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/*******************************************************************************
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* Handler to save MC settings before "System Suspend" to TZDRAM
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*
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* Implemented by Tegra common memctrl_v2 driver under common/drivers/memctrl
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******************************************************************************/
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void tegra_mc_save_context(uint64_t mc_ctx_addr);
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/*******************************************************************************
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* Handler to program the scratch registers with TZDRAM settings for the
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* resume firmware.
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*
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* Implemented by SoCs under tegra/soc/txxx
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******************************************************************************/
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void plat_memctrl_tzdram_setup(uint64_t phys_base, uint64_t size_in_bytes);
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#endif /* __ASSEMBLER__ */
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#endif /* MEMCTRL_V2_H */
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