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Andre Przywara 5f5d076387 Neoverse N1: Introduce workaround for Neoverse N1 erratum 1315703 
Neoverse N1 erratum 1315703 is a Cat A (rare) erratum [1], present in
older revisions of the Neoverse N1 processor core.
The workaround is to set a bit in the implementation defined CPUACTLR2_EL1
system register, which will disable the load-bypass-store feature.

[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdocpjdoc-466751330-1032/index.html

Change-Id: I5c708dbe0efa4daa0bcb6bd9622c5efe19c03af9
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
 		2019-06-06 14:27:37 +01:00
..
aarch32 cpus: Fix Cortex-A12 MIDR mask 2019-04-08 12:47:48 +02:00
aarch64 Neoverse N1: Introduce workaround for Neoverse N1 erratum 1315703 2019-06-06 14:27:37 +01:00
errata_report.h Sanitise includes across codebase 2019-01-04 10:43:17 +00:00
wa_cve_2017_5715.h Fix MISRA defects in workaround and errata framework 2018-10-29 14:41:48 +00:00
wa_cve_2018_3639.h Fix MISRA defects in workaround and errata framework 2018-10-29 14:41:48 +00:00