Vikram Kanigiri e3616819a9 Tegra: Perform cache maintenance on video carveout memory ... Currently, the non-overlapping video memory carveout region is cleared after disabling the MMU at EL3. If at any exception level the carveout region is being marked as cacheable, this zeroing of memory will not have an affect on the cached lines. Hence, we first invalidate the dirty lines and update the memory and invalidate again so that both caches and memory is zeroed out. Change-Id: If3b2d139ab7227f6799c0911d59e079849dc86aa		2015-09-14 22:09:40 +01:00
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arm	Separate CSS security setup from SOC security setup	2015-09-11 11:50:26 +01:00
common	PSCI: Add deprecated API for SPD when compatibility is disabled	2015-08-13 23:48:06 +01:00
compat	PSCI: Implement platform compatibility layer	2015-08-13 20:08:19 +01:00
mediatek	Use unified bakery locks API in Mediatek port	2015-09-11 16:20:01 +01:00
nvidia/tegra	Tegra: Perform cache maintenance on video carveout memory	2015-09-14 22:09:40 +01:00