119 lines
2.0 KiB
C
119 lines
2.0 KiB
C
/*
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* Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <platform_def.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <drivers/st/stm32mp_clkfunc.h>
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#include <plat/common/platform.h>
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uintptr_t plat_get_ns_image_entrypoint(void)
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{
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return BL33_BASE;
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}
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unsigned int plat_get_syscnt_freq2(void)
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{
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return read_cntfrq_el0();
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}
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static uintptr_t boot_ctx_address;
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void stm32mp_save_boot_ctx_address(uintptr_t address)
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{
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boot_ctx_address = address;
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}
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uintptr_t stm32mp_get_boot_ctx_address(void)
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{
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return boot_ctx_address;
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}
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uintptr_t stm32mp_ddrctrl_base(void)
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{
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static uintptr_t ddrctrl_base;
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if (ddrctrl_base == 0) {
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ddrctrl_base = dt_get_ddrctrl_base();
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assert(ddrctrl_base == DDRCTRL_BASE);
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}
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return ddrctrl_base;
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}
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uintptr_t stm32mp_ddrphyc_base(void)
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{
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static uintptr_t ddrphyc_base;
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if (ddrphyc_base == 0) {
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ddrphyc_base = dt_get_ddrphyc_base();
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assert(ddrphyc_base == DDRPHYC_BASE);
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}
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return ddrphyc_base;
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}
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uintptr_t stm32mp_pwr_base(void)
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{
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static uintptr_t pwr_base;
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if (pwr_base == 0) {
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pwr_base = dt_get_pwr_base();
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assert(pwr_base == PWR_BASE);
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}
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return pwr_base;
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}
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uintptr_t stm32mp_rcc_base(void)
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{
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static uintptr_t rcc_base;
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if (rcc_base == 0) {
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rcc_base = fdt_rcc_read_addr();
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assert(rcc_base == RCC_BASE);
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}
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return rcc_base;
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}
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bool stm32mp_lock_available(void)
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{
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const uint32_t c_m_bits = SCTLR_M_BIT | SCTLR_C_BIT;
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/* The spinlocks are used only when MMU and data cache are enabled */
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return (read_sctlr() & c_m_bits) == c_m_bits;
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}
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uintptr_t stm32_get_gpio_bank_base(unsigned int bank)
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{
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if (bank == GPIO_BANK_Z) {
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return GPIOZ_BASE;
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}
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assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K);
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return GPIOA_BASE + (bank * GPIO_BANK_OFFSET);
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}
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uint32_t stm32_get_gpio_bank_offset(unsigned int bank)
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{
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if (bank == GPIO_BANK_Z) {
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return 0;
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}
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assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K);
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return bank * GPIO_BANK_OFFSET;
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}
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