65 lines
2.0 KiB
C
65 lines
2.0 KiB
C
/*
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* Copyright (c) 2022, MediaTek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLAT_DFD_H
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#define PLAT_DFD_H
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#include <arch_helpers.h>
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#include <lib/mmio.h>
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#include <platform_def.h>
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#define sync_writel(addr, val) do { mmio_write_32((addr), (val)); \
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dsbsy(); \
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} while (0)
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#define PLAT_MTK_DFD_SETUP_MAGIC (0x99716150)
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#define PLAT_MTK_DFD_READ_MAGIC (0x99716151)
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#define PLAT_MTK_DFD_WRITE_MAGIC (0x99716152)
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#define MCU_BIU_BASE (MCUCFG_BASE)
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#define MISC1_CFG_BASE (MCU_BIU_BASE + 0xA040)
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#define DFD_INTERNAL_CTL (MISC1_CFG_BASE + 0x00)
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#define DFD_INTERNAL_PWR_ON (MISC1_CFG_BASE + 0x08)
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#define DFD_CHAIN_LENGTH0 (MISC1_CFG_BASE + 0x0C)
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#define DFD_INTERNAL_SHIFT_CLK_RATIO (MISC1_CFG_BASE + 0x10)
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#define DFD_INTERNAL_TEST_SO_0 (MISC1_CFG_BASE + 0x28)
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#define DFD_INTERNAL_NUM_OF_TEST_SO_GROUP (MISC1_CFG_BASE + 0x30)
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#define DFD_V30_CTL (MISC1_CFG_BASE + 0x48)
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#define DFD_V30_BASE_ADDR (MISC1_CFG_BASE + 0x4C)
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#define DFD_TEST_SI_0 (MISC1_CFG_BASE + 0x58)
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#define DFD_TEST_SI_1 (MISC1_CFG_BASE + 0x5C)
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#define DFD_HW_TRIGGER_MASK (MISC1_CFG_BASE + 0xBC)
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#define DFD_V35_ENALBE (MCU_BIU_BASE + 0xA0A8)
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#define DFD_V35_TAP_NUMBER (MCU_BIU_BASE + 0xA0AC)
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#define DFD_V35_TAP_EN (MCU_BIU_BASE + 0xA0B0)
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#define DFD_V35_SEQ0_0 (MCU_BIU_BASE + 0xA0C0)
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#define DFD_V35_SEQ0_1 (MCU_BIU_BASE + 0xA0C4)
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#define DFD_CACHE_DUMP_ENABLE (1U)
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#define DFD_PARITY_ERR_TRIGGER (2U)
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#define MCUSYS_DFD_MAP (0x10001390)
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#define WDT_DEBUG_CTL (0x10007048)
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#define WDT_DEBUG_CTL_VAL_0 (0x950603A0)
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#define DFD_INTERNAL_TEST_SO_0_VAL (0x3B)
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#define DFD_TEST_SI_0_VAL (0x108)
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#define DFD_TEST_SI_1_VAL (0x20200000)
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#define WDT_DEBUG_CTL_VAL_1 (0x95063E80)
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#define DFD_V35_TAP_NUMBER_VAL (0xA)
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#define DFD_V35_TAP_EN_VAL (0x3FF)
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#define DFD_V35_SEQ0_0_VAL (0x63668820)
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#define DFD_HW_TRIGGER_MASK_VAL (0xC)
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void dfd_resume(void);
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uint64_t dfd_smc_dispatcher(uint64_t arg0, uint64_t arg1,
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uint64_t arg2, uint64_t arg3);
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#endif /* PLAT_DFD_H */
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