163 lines
3.8 KiB
C
163 lines
3.8 KiB
C
/*
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <amu.h>
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#include <amu_private.h>
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#include <arch.h>
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#include <arch_helpers.h>
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#include <platform.h>
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#include <pubsub_events.h>
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#define AMU_GROUP0_NR_COUNTERS 4
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struct amu_ctx {
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uint64_t group0_cnts[AMU_GROUP0_NR_COUNTERS];
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uint64_t group1_cnts[AMU_GROUP1_NR_COUNTERS];
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};
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static struct amu_ctx amu_ctxs[PLATFORM_CORE_COUNT];
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int amu_supported(void)
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{
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uint64_t features;
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features = read_id_pfr0() >> ID_PFR0_AMU_SHIFT;
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return (features & ID_PFR0_AMU_MASK) == 1;
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}
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void amu_enable(int el2_unused)
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{
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if (!amu_supported())
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return;
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if (el2_unused) {
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uint64_t v;
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/*
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* Non-secure access from EL0 or EL1 to the Activity Monitor
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* registers do not trap to EL2.
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*/
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v = read_hcptr();
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v &= ~TAM_BIT;
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write_hcptr(v);
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}
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/* Enable group 0 counters */
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write_amcntenset0(AMU_GROUP0_COUNTERS_MASK);
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/* Enable group 1 counters */
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write_amcntenset1(AMU_GROUP1_COUNTERS_MASK);
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}
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/* Read the group 0 counter identified by the given `idx`. */
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uint64_t amu_group0_cnt_read(int idx)
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{
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assert(amu_supported());
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assert(idx >= 0 && idx < AMU_GROUP0_NR_COUNTERS);
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return amu_group0_cnt_read_internal(idx);
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}
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/* Write the group 0 counter identified by the given `idx` with `val`. */
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void amu_group0_cnt_write(int idx, uint64_t val)
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{
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assert(amu_supported());
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assert(idx >= 0 && idx < AMU_GROUP0_NR_COUNTERS);
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amu_group0_cnt_write_internal(idx, val);
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isb();
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}
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/* Read the group 1 counter identified by the given `idx`. */
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uint64_t amu_group1_cnt_read(int idx)
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{
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assert(amu_supported());
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assert(idx >= 0 && idx < AMU_GROUP1_NR_COUNTERS);
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return amu_group1_cnt_read_internal(idx);
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}
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/* Write the group 1 counter identified by the given `idx` with `val`. */
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void amu_group1_cnt_write(int idx, uint64_t val)
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{
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assert(amu_supported());
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assert(idx >= 0 && idx < AMU_GROUP1_NR_COUNTERS);
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amu_group1_cnt_write_internal(idx, val);
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isb();
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}
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void amu_group1_set_evtype(int idx, unsigned int val)
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{
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assert(amu_supported());
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assert(idx >= 0 && idx < AMU_GROUP1_NR_COUNTERS);
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amu_group1_set_evtype_internal(idx, val);
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isb();
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}
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static void *amu_context_save(const void *arg)
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{
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struct amu_ctx *ctx;
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int i;
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if (!amu_supported())
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return (void *)-1;
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ctx = &amu_ctxs[plat_my_core_pos()];
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/* Assert that group 0 counter configuration is what we expect */
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assert(read_amcntenset0() == AMU_GROUP0_COUNTERS_MASK &&
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read_amcntenset1() == AMU_GROUP1_COUNTERS_MASK);
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/*
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* Disable group 0 counters to avoid other observers like SCP sampling
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* counter values from the future via the memory mapped view.
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*/
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write_amcntenclr0(AMU_GROUP0_COUNTERS_MASK);
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write_amcntenclr1(AMU_GROUP1_COUNTERS_MASK);
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isb();
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for (i = 0; i < AMU_GROUP0_NR_COUNTERS; i++)
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ctx->group0_cnts[i] = amu_group0_cnt_read(i);
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for (i = 0; i < AMU_GROUP1_NR_COUNTERS; i++)
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ctx->group1_cnts[i] = amu_group1_cnt_read(i);
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return 0;
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}
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static void *amu_context_restore(const void *arg)
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{
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struct amu_ctx *ctx;
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uint64_t features;
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int i;
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features = read_id_pfr0() >> ID_PFR0_AMU_SHIFT;
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if ((features & ID_PFR0_AMU_MASK) != 1)
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return (void *)-1;
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ctx = &amu_ctxs[plat_my_core_pos()];
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/* Counters were disabled in `amu_context_save()` */
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assert(read_amcntenset0() == 0 && read_amcntenset1() == 0);
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/* Restore group 0 counters */
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for (i = 0; i < AMU_GROUP0_NR_COUNTERS; i++)
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amu_group0_cnt_write(i, ctx->group0_cnts[i]);
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for (i = 0; i < AMU_GROUP1_NR_COUNTERS; i++)
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amu_group1_cnt_write(i, ctx->group1_cnts[i]);
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/* Enable group 0 counters */
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write_amcntenset0(AMU_GROUP0_COUNTERS_MASK);
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/* Enable group 1 counters */
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write_amcntenset1(AMU_GROUP1_COUNTERS_MASK);
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return 0;
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}
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SUBSCRIBE_TO_EVENT(psci_suspend_pwrdown_start, amu_context_save);
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SUBSCRIBE_TO_EVENT(psci_suspend_pwrdown_finish, amu_context_restore);
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