193 lines
5.0 KiB
ArmAsm
193 lines
5.0 KiB
ArmAsm
/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <assert_macros.S>
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#include <cortex_a72.h>
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#include <cpu_macros.S>
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#include <debug.h>
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/* ---------------------------------------------
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* Disable all types of L2 prefetches.
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* ---------------------------------------------
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*/
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func cortex_a72_disable_l2_prefetch
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ldcopr16 r0, r1, CPUECTLR
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orr64_imm r0, r1, CPUECTLR_DIS_TWD_ACC_PFTCH_BIT
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bic64_imm r0, r1, (CPUECTLR_L2_IPFTCH_DIST_MASK | \
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CPUECTLR_L2_DPFTCH_DIST_MASK)
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stcopr16 r0, r1, CPUECTLR
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isb
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bx lr
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endfunc cortex_a72_disable_l2_prefetch
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/* ---------------------------------------------
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* Disable the load-store hardware prefetcher.
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* ---------------------------------------------
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*/
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func cortex_a72_disable_hw_prefetcher
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ldcopr16 r0, r1, CPUACTLR
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orr64_imm r0, r1, CPUACTLR_DISABLE_L1_DCACHE_HW_PFTCH
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stcopr16 r0, r1, CPUACTLR
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isb
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dsb ish
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bx lr
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endfunc cortex_a72_disable_hw_prefetcher
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/* ---------------------------------------------
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* Disable intra-cluster coherency
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* Clobbers: r0-r1
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* ---------------------------------------------
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*/
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func cortex_a72_disable_smp
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ldcopr16 r0, r1, CPUECTLR
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bic64_imm r0, r1, CPUECTLR_SMP_BIT
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stcopr16 r0, r1, CPUECTLR
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bx lr
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endfunc cortex_a72_disable_smp
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/* ---------------------------------------------
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* Disable debug interfaces
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* ---------------------------------------------
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*/
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func cortex_a72_disable_ext_debug
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mov r0, #1
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stcopr r0, DBGOSDLR
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isb
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dsb sy
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bx lr
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endfunc cortex_a72_disable_ext_debug
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/* -------------------------------------------------
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* The CPU Ops reset function for Cortex-A72.
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* -------------------------------------------------
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*/
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func cortex_a72_reset_func
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/* ---------------------------------------------
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* Enable the SMP bit.
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* ---------------------------------------------
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*/
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ldcopr16 r0, r1, CPUECTLR
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orr64_imm r0, r1, CPUECTLR_SMP_BIT
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stcopr16 r0, r1, CPUECTLR
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isb
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bx lr
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endfunc cortex_a72_reset_func
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/* ----------------------------------------------------
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* The CPU Ops core power down function for Cortex-A72.
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* ----------------------------------------------------
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*/
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func cortex_a72_core_pwr_dwn
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push {r12, lr}
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/* Assert if cache is enabled */
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#if ASM_ASSERTION
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ldcopr r0, SCTLR
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tst r0, #SCTLR_C_BIT
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ASM_ASSERT(eq)
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#endif
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/* ---------------------------------------------
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* Disable the L2 prefetches.
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* ---------------------------------------------
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*/
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bl cortex_a72_disable_l2_prefetch
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/* ---------------------------------------------
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* Disable the load-store hardware prefetcher.
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* ---------------------------------------------
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*/
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bl cortex_a72_disable_hw_prefetcher
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/* ---------------------------------------------
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* Flush L1 caches.
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* ---------------------------------------------
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*/
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mov r0, #DC_OP_CISW
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bl dcsw_op_level1
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/* ---------------------------------------------
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* Come out of intra cluster coherency
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* ---------------------------------------------
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*/
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bl cortex_a72_disable_smp
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/* ---------------------------------------------
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* Force the debug interfaces to be quiescent
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* ---------------------------------------------
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*/
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pop {r12, lr}
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b cortex_a72_disable_ext_debug
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endfunc cortex_a72_core_pwr_dwn
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/* -------------------------------------------------------
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* The CPU Ops cluster power down function for Cortex-A72.
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* -------------------------------------------------------
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*/
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func cortex_a72_cluster_pwr_dwn
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push {r12, lr}
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/* Assert if cache is enabled */
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#if ASM_ASSERTION
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ldcopr r0, SCTLR
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tst r0, #SCTLR_C_BIT
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ASM_ASSERT(eq)
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#endif
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/* ---------------------------------------------
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* Disable the L2 prefetches.
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* ---------------------------------------------
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*/
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bl cortex_a72_disable_l2_prefetch
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/* ---------------------------------------------
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* Disable the load-store hardware prefetcher.
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* ---------------------------------------------
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*/
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bl cortex_a72_disable_hw_prefetcher
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#if !SKIP_A72_L1_FLUSH_PWR_DWN
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/* ---------------------------------------------
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* Flush L1 caches.
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* ---------------------------------------------
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*/
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mov r0, #DC_OP_CISW
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bl dcsw_op_level1
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#endif
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/* ---------------------------------------------
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* Disable the optional ACP.
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* ---------------------------------------------
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*/
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bl plat_disable_acp
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/* -------------------------------------------------
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* Flush the L2 caches.
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* -------------------------------------------------
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*/
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mov r0, #DC_OP_CISW
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bl dcsw_op_level2
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/* ---------------------------------------------
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* Come out of intra cluster coherency
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* ---------------------------------------------
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*/
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bl cortex_a72_disable_smp
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/* ---------------------------------------------
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* Force the debug interfaces to be quiescent
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* ---------------------------------------------
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*/
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pop {r12, lr}
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b cortex_a72_disable_ext_debug
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endfunc cortex_a72_cluster_pwr_dwn
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declare_cpu_ops cortex_a72, CORTEX_A72_MIDR, \
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cortex_a72_reset_func, \
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cortex_a72_core_pwr_dwn, \
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cortex_a72_cluster_pwr_dwn
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