90 lines
2.7 KiB
ArmAsm
90 lines
2.7 KiB
ArmAsm
/*
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* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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.globl read_icc_sre_el1
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.globl read_icc_sre_el2
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.globl read_icc_sre_el3
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.globl write_icc_sre_el1
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.globl write_icc_sre_el2
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.globl write_icc_sre_el3
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.globl write_icc_pmr_el1
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/*
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* Register definitions used by GCC for GICv3 access.
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* These are defined by ARMCC, so keep them in the GCC specific code for now.
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*/
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#define ICC_SRE_EL1 S3_0_C12_C12_5
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#define ICC_SRE_EL2 S3_4_C12_C9_5
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#define ICC_SRE_EL3 S3_6_C12_C12_5
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#define ICC_CTLR_EL1 S3_0_C12_C12_4
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#define ICC_CTLR_EL3 S3_6_C12_C12_4
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#define ICC_PMR_EL1 S3_0_C4_C6_0
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.section .text, "ax"; .align 3
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read_icc_sre_el1:; .type read_icc_sre_el1, %function
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mrs x0, ICC_SRE_EL1
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ret
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read_icc_sre_el2:; .type read_icc_sre_el2, %function
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mrs x0, ICC_SRE_EL2
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ret
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read_icc_sre_el3:; .type read_icc_sre_el3, %function
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mrs x0, ICC_SRE_EL3
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ret
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write_icc_sre_el1:; .type write_icc_sre_el1, %function
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msr ICC_SRE_EL1, x0
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isb
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ret
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write_icc_sre_el2:; .type write_icc_sre_el2, %function
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msr ICC_SRE_EL2, x0
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isb
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ret
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write_icc_sre_el3:; .type write_icc_sre_el3, %function
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msr ICC_SRE_EL3, x0
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isb
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ret
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write_icc_pmr_el1:; .type write_icc_pmr_el1, %function
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msr ICC_PMR_EL1, x0
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isb
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ret
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