201 lines
7.2 KiB
C
201 lines
7.2 KiB
C
/*
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* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __GIC_H__
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#define __GIC_H__
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#define MAX_SPIS 480
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#define MAX_PPIS 14
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#define MAX_SGIS 16
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#define GRP0 0
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#define GRP1 1
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#define MAX_PRI_VAL 0xff
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#define ENABLE_GRP0 (1 << 0)
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#define ENABLE_GRP1 (1 << 1)
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/* Distributor interface definitions */
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#define GICD_CTLR 0x0
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#define GICD_TYPER 0x4
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#define GICD_IGROUPR 0x80
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#define GICD_ISENABLER 0x100
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#define GICD_ICENABLER 0x180
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#define GICD_ISPENDR 0x200
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#define GICD_ICPENDR 0x280
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#define GICD_ISACTIVER 0x300
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#define GICD_ICACTIVER 0x380
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#define GICD_IPRIORITYR 0x400
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#define GICD_ITARGETSR 0x800
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#define GICD_ICFGR 0xC00
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#define GICD_SGIR 0xF00
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#define GICD_CPENDSGIR 0xF10
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#define GICD_SPENDSGIR 0xF20
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#define IGROUPR_SHIFT 5
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#define ISENABLER_SHIFT 5
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#define ICENABLER_SHIFT ISENABLER_SHIFT
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#define ISPENDR_SHIFT 5
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#define ICPENDR_SHIFT ISPENDR_SHIFT
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#define ISACTIVER_SHIFT 5
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#define ICACTIVER_SHIFT ISACTIVER_SHIFT
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#define IPRIORITYR_SHIFT 2
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#define ITARGETSR_SHIFT 2
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#define ICFGR_SHIFT 4
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#define CPENDSGIR_SHIFT 2
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#define SPENDSGIR_SHIFT CPENDSGIR_SHIFT
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/* GICD_TYPER bit definitions */
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#define IT_LINES_NO_MASK 0x1f
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/* Physical CPU Interface registers */
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#define GICC_CTLR 0x0
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#define GICC_PMR 0x4
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#define GICC_BPR 0x8
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#define GICC_IAR 0xC
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#define GICC_EOIR 0x10
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#define GICC_RPR 0x14
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#define GICC_HPPIR 0x18
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#define GICC_IIDR 0xFC
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#define GICC_DIR 0x1000
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#define GICC_PRIODROP GICC_EOIR
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/* GICC_CTLR bit definitions */
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#define EOI_MODE_NS (1 << 10)
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#define EOI_MODE_S (1 << 9)
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#define IRQ_BYP_DIS_GRP1 (1 << 8)
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#define FIQ_BYP_DIS_GRP1 (1 << 7)
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#define IRQ_BYP_DIS_GRP0 (1 << 6)
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#define FIQ_BYP_DIS_GRP0 (1 << 5)
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#define CBPR (1 << 4)
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#define FIQ_EN (1 << 3)
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#define ACK_CTL (1 << 2)
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/* GICC_IIDR bit masks and shifts */
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#define GICC_IIDR_PID_SHIFT 20
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#define GICC_IIDR_ARCH_SHIFT 16
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#define GICC_IIDR_REV_SHIFT 12
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#define GICC_IIDR_IMP_SHIFT 0
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#define GICC_IIDR_PID_MASK 0xfff
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#define GICC_IIDR_ARCH_MASK 0xf
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#define GICC_IIDR_REV_MASK 0xf
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#define GICC_IIDR_IMP_MASK 0xfff
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/* HYP view virtual CPU Interface registers */
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#define GICH_CTL 0x0
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#define GICH_VTR 0x4
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#define GICH_ELRSR0 0x30
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#define GICH_ELRSR1 0x34
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#define GICH_APR0 0xF0
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#define GICH_LR_BASE 0x100
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/* Virtual CPU Interface registers */
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#define GICV_CTL 0x0
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#define GICV_PRIMASK 0x4
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#define GICV_BP 0x8
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#define GICV_INTACK 0xC
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#define GICV_EOI 0x10
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#define GICV_RUNNINGPRI 0x14
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#define GICV_HIGHESTPEND 0x18
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#define GICV_DEACTIVATE 0x1000
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/* GICv3 Re-distributor interface registers & shifts */
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#define GICR_PCPUBASE_SHIFT 0x11
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#define GICR_WAKER 0x14
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/* GICR_WAKER bit definitions */
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#define WAKER_CA (1UL << 2)
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#define WAKER_PS (1UL << 1)
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/* GICv3 ICC_SRE register bit definitions*/
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#define ICC_SRE_EN (1UL << 3)
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#define ICC_SRE_SRE (1UL << 0)
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#ifndef __ASSEMBLY__
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#include <gic_v2.h>
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#include <gic_v3.h>
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/*******************************************************************************
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* Function prototypes
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******************************************************************************/
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extern unsigned int gicd_read_igroupr(unsigned int, unsigned int);
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extern unsigned int gicd_read_isenabler(unsigned int, unsigned int);
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extern unsigned int gicd_read_icenabler(unsigned int, unsigned int);
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extern unsigned int gicd_read_ispendr(unsigned int, unsigned int);
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extern unsigned int gicd_read_icpendr(unsigned int, unsigned int);
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extern unsigned int gicd_read_isactiver(unsigned int, unsigned int);
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extern unsigned int gicd_read_icactiver(unsigned int, unsigned int);
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extern unsigned int gicd_read_ipriorityr(unsigned int, unsigned int);
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extern unsigned int gicd_read_itargetsr(unsigned int, unsigned int);
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extern unsigned int gicd_read_icfgr(unsigned int, unsigned int);
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extern unsigned int gicd_read_cpendsgir(unsigned int, unsigned int);
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extern unsigned int gicd_read_spendsgir(unsigned int, unsigned int);
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extern void gicd_write_igroupr(unsigned int, unsigned int, unsigned int);
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extern void gicd_write_isenabler(unsigned int, unsigned int, unsigned int);
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extern void gicd_write_icenabler(unsigned int, unsigned int, unsigned int);
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extern void gicd_write_ispendr(unsigned int, unsigned int, unsigned int);
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extern void gicd_write_icpendr(unsigned int, unsigned int, unsigned int);
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extern void gicd_write_isactiver(unsigned int, unsigned int, unsigned int);
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extern void gicd_write_icactiver(unsigned int, unsigned int, unsigned int);
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extern void gicd_write_ipriorityr(unsigned int, unsigned int, unsigned int);
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extern void gicd_write_itargetsr(unsigned int, unsigned int, unsigned int);
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extern void gicd_write_icfgr(unsigned int, unsigned int, unsigned int);
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extern void gicd_write_cpendsgir(unsigned int, unsigned int, unsigned int);
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extern void gicd_write_spendsgir(unsigned int, unsigned int, unsigned int);
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extern unsigned int gicd_get_igroupr(unsigned int, unsigned int);
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extern void gicd_set_igroupr(unsigned int, unsigned int);
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extern void gicd_clr_igroupr(unsigned int, unsigned int);
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extern void gicd_set_isenabler(unsigned int, unsigned int);
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extern void gicd_set_icenabler(unsigned int, unsigned int);
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extern void gicd_set_ispendr(unsigned int, unsigned int);
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extern void gicd_set_icpendr(unsigned int, unsigned int);
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extern void gicd_set_isactiver(unsigned int, unsigned int);
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extern void gicd_set_icactiver(unsigned int, unsigned int);
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extern void gicd_set_ipriorityr(unsigned int, unsigned int, unsigned int);
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extern void gicd_set_itargetsr(unsigned int, unsigned int, unsigned int);
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/* GICv3 functions */
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extern unsigned int read_icc_sre_el1(void);
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extern unsigned int read_icc_sre_el2(void);
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extern unsigned int read_icc_sre_el3(void);
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extern void write_icc_sre_el1(unsigned int);
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extern void write_icc_sre_el2(unsigned int);
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extern void write_icc_sre_el3(unsigned int);
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extern void write_icc_pmr_el1(unsigned int);
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#endif /*__ASSEMBLY__*/
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#endif /* __GIC_H__ */
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