217 lines
5.3 KiB
ArmAsm
217 lines
5.3 KiB
ArmAsm
/*
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* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch.h>
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#include <bl_common.h>
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#include <bl1.h>
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#include <platform.h>
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#include <runtime_svc.h>
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.globl early_exceptions
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.section .text, "ax"; .align 11
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/* -----------------------------------------------------
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* Very simple exception handlers used by BL1 and BL2.
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* Apart from one SMC exception all other traps loop
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* endlessly.
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* -----------------------------------------------------
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*/
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.align 7
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early_exceptions:
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/* -----------------------------------------------------
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* Current EL with SP0 : 0x0 - 0x180
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* -----------------------------------------------------
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*/
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SynchronousExceptionSP0:
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mov x0, #SYNC_EXCEPTION_SP_EL0
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bl plat_report_exception
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b SynchronousExceptionSP0
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.align 7
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IrqSP0:
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mov x0, #IRQ_SP_EL0
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bl plat_report_exception
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b IrqSP0
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.align 7
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FiqSP0:
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mov x0, #FIQ_SP_EL0
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bl plat_report_exception
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b FiqSP0
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.align 7
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SErrorSP0:
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mov x0, #SERROR_SP_EL0
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bl plat_report_exception
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b SErrorSP0
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/* -----------------------------------------------------
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* Current EL with SPx: 0x200 - 0x380
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* -----------------------------------------------------
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*/
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.align 7
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SynchronousExceptionSPx:
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mov x0, #SYNC_EXCEPTION_SP_ELX
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bl plat_report_exception
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b SynchronousExceptionSPx
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.align 7
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IrqSPx:
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mov x0, #IRQ_SP_ELX
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bl plat_report_exception
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b IrqSPx
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.align 7
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FiqSPx:
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mov x0, #FIQ_SP_ELX
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bl plat_report_exception
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b FiqSPx
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.align 7
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SErrorSPx:
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mov x0, #SERROR_SP_ELX
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bl plat_report_exception
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b SErrorSPx
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/* -----------------------------------------------------
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* Lower EL using AArch64 : 0x400 - 0x580
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* -----------------------------------------------------
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*/
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.align 7
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SynchronousExceptionA64:
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/* ---------------------------------------------
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* Only a single SMC exception from BL2 to ask
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* BL1 to pass EL3 control to BL31 is expected
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* here.
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* ---------------------------------------------
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*/
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sub sp, sp, #0x40
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stp x0, x1, [sp, #0x0]
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stp x2, x3, [sp, #0x10]
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stp x4, x5, [sp, #0x20]
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stp x6, x7, [sp, #0x30]
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mov x19, x0
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mov x20, x1
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mov x21, x2
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mov x0, #SYNC_EXCEPTION_AARCH64
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bl plat_report_exception
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bl read_esr
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ubfx x1, x0, #ESR_EC_SHIFT, #ESR_EC_LENGTH
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cmp x1, #EC_AARCH64_SMC
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b.ne panic
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mov x1, #RUN_IMAGE
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cmp x19, x1
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b.ne panic
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mov x0, x20
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mov x1, x21
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mov x2, x3
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mov x3, x4
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bl display_boot_progress
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mov x0, x20
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bl write_elr
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mov x0, x21
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bl write_spsr
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ubfx x0, x21, #MODE_EL_SHIFT, #2
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cmp x0, #MODE_EL3
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b.ne skip_mmu_teardown
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/* ---------------------------------------------
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* If BL31 is to be executed in EL3 as well
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* then turn off the MMU so that it can perform
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* its own setup. TODO: Assuming flat mapped
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* translations here. Also all should go into a
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* separate MMU teardown function
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* ---------------------------------------------
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*/
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mov x1, #(SCTLR_M_BIT | SCTLR_C_BIT | SCTLR_I_BIT)
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bl read_sctlr
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bic x0, x0, x1
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bl write_sctlr
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mov x0, #DCCISW
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bl dcsw_op_all
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bl tlbialle3
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skip_mmu_teardown:
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ldp x6, x7, [sp, #0x30]
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ldp x4, x5, [sp, #0x20]
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ldp x2, x3, [sp, #0x10]
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ldp x0, x1, [sp, #0x0]
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add sp, sp, #0x40
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eret
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panic:
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b panic
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.align 7
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IrqA64:
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mov x0, #IRQ_AARCH64
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bl plat_report_exception
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b IrqA64
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.align 7
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FiqA64:
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mov x0, #FIQ_AARCH64
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bl plat_report_exception
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b FiqA64
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.align 7
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SErrorA64:
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mov x0, #SERROR_AARCH64
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bl plat_report_exception
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b SErrorA64
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/* -----------------------------------------------------
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* Lower EL using AArch32 : 0x0 - 0x180
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* -----------------------------------------------------
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*/
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.align 7
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SynchronousExceptionA32:
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mov x0, #SYNC_EXCEPTION_AARCH32
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bl plat_report_exception
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b SynchronousExceptionA32
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.align 7
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IrqA32:
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mov x0, #IRQ_AARCH32
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bl plat_report_exception
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b IrqA32
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.align 7
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FiqA32:
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mov x0, #FIQ_AARCH32
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bl plat_report_exception
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b FiqA32
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.align 7
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SErrorA32:
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mov x0, #SERROR_AARCH32
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bl plat_report_exception
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b SErrorA32
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