110 lines
3.6 KiB
ArmAsm
110 lines
3.6 KiB
ArmAsm
/*
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* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <platform.h>
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OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
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OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
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MEMORY {
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RAM (rwx): ORIGIN = TZRAM_BASE, LENGTH = TZRAM_SIZE
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}
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SECTIONS
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{
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. = BL2_BASE;
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ASSERT(. == ALIGN(4096),
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"BL2_BASE address is not aligned on a page boundary.")
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ro . : {
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__RO_START__ = .;
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*bl2_entrypoint.o(.text)
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*(.text)
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*(.rodata*)
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__RO_END_UNALIGNED__ = .;
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/*
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* Memory page(s) mapped to this section will be marked as
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* read-only, executable. No RW data from the next section must
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* creep in. Ensure the rest of the current memory page is unused.
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*/
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. = NEXT(4096);
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__RO_END__ = .;
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} >RAM
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.data . : {
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__DATA_START__ = .;
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*(.data)
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__DATA_END__ = .;
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} >RAM
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stacks (NOLOAD) : {
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__STACKS_START__ = .;
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*(tzfw_normal_stacks)
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__STACKS_END__ = .;
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} >RAM
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/*
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* The .bss section gets initialised to 0 at runtime.
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* Its base address must be 16-byte aligned.
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*/
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.bss : ALIGN(16) {
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__BSS_START__ = .;
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*(SORT_BY_ALIGNMENT(.bss))
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*(COMMON)
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__BSS_END__ = .;
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} >RAM
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/*
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* The base address of the coherent memory section must be page-aligned (4K)
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* to guarantee that the coherent data are stored on their own pages and
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* are not mixed with normal data. This is required to set up the correct
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* memory attributes for the coherent data page tables.
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*/
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coherent_ram (NOLOAD) : ALIGN(4096) {
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__COHERENT_RAM_START__ = .;
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*(tzfw_coherent_mem)
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__COHERENT_RAM_END_UNALIGNED__ = .;
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/*
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* Memory page(s) mapped to this section will be marked
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* as device memory. No other unexpected data must creep in.
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* Ensure the rest of the current memory page is unused.
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*/
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. = NEXT(4096);
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__COHERENT_RAM_END__ = .;
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} >RAM
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__BL2_END__ = .;
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__BSS_SIZE__ = SIZEOF(.bss);
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__COHERENT_RAM_UNALIGNED_SIZE__ =
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__COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
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}
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