509 lines
16 KiB
C
509 lines
16 KiB
C
/*
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* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <stdio.h>
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#include <string.h>
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#include <assert.h>
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#include <arch_helpers.h>
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#include <console.h>
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#include <platform.h>
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#include <psci.h>
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#include <psci_private.h>
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typedef int (*afflvl_suspend_handler)(unsigned long,
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aff_map_node *,
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unsigned long,
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unsigned long,
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unsigned int);
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/*******************************************************************************
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* The next three functions implement a handler for each supported affinity
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* level which is called when that affinity level is about to be suspended.
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******************************************************************************/
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static int psci_afflvl0_suspend(unsigned long mpidr,
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aff_map_node *cpu_node,
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unsigned long ns_entrypoint,
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unsigned long context_id,
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unsigned int power_state)
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{
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unsigned int index, plat_state;
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unsigned long psci_entrypoint, sctlr = read_sctlr();
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int rc = PSCI_E_SUCCESS;
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/* Sanity check to safeguard against data corruption */
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assert(cpu_node->level == MPIDR_AFFLVL0);
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/*
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* Generic management: Store the re-entry information for the
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* non-secure world
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*/
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index = cpu_node->data;
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rc = psci_set_ns_entry_info(index, ns_entrypoint, context_id);
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if (rc != PSCI_E_SUCCESS)
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return rc;
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/*
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* Arch. management: Save the secure context, flush the
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* L1 caches and exit intra-cluster coherency et al
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*/
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psci_secure_context[index].sctlr = read_sctlr();
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psci_secure_context[index].scr = read_scr();
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psci_secure_context[index].cptr = read_cptr();
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psci_secure_context[index].cpacr = read_cpacr();
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psci_secure_context[index].cntfrq = read_cntfrq_el0();
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psci_secure_context[index].mair = read_mair();
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psci_secure_context[index].tcr = read_tcr();
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psci_secure_context[index].ttbr = read_ttbr0();
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psci_secure_context[index].vbar = read_vbar();
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psci_secure_context[index].pstate =
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read_daif() & (DAIF_ABT_BIT | DAIF_DBG_BIT);
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/* Set the secure world (EL3) re-entry point after BL1 */
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psci_entrypoint = (unsigned long) psci_aff_suspend_finish_entry;
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/*
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* Arch. management. Perform the necessary steps to flush all
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* cpu caches.
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*
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* TODO: This power down sequence varies across cpus so it needs to be
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* abstracted out on the basis of the MIDR like in cpu_reset_handler().
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* Do the bare minimal for the time being. Fix this before porting to
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* Cortex models.
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*/
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sctlr &= ~SCTLR_C_BIT;
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write_sctlr(sctlr);
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/*
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* CAUTION: This flush to the level of unification makes an assumption
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* about the cache hierarchy at affinity level 0 (cpu) in the platform.
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* Ideally the platform should tell psci which levels to flush to exit
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* coherency.
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*/
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dcsw_op_louis(DCCISW);
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/*
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* Plat. management: Allow the platform to perform the
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* necessary actions to turn off this cpu e.g. set the
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* platform defined mailbox with the psci entrypoint,
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* program the power controller etc.
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*/
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if (psci_plat_pm_ops->affinst_suspend) {
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plat_state = psci_get_aff_phys_state(cpu_node);
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rc = psci_plat_pm_ops->affinst_suspend(mpidr,
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psci_entrypoint,
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ns_entrypoint,
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cpu_node->level,
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plat_state);
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}
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return rc;
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}
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static int psci_afflvl1_suspend(unsigned long mpidr,
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aff_map_node *cluster_node,
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unsigned long ns_entrypoint,
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unsigned long context_id,
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unsigned int power_state)
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{
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int rc = PSCI_E_SUCCESS;
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unsigned int plat_state;
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unsigned long psci_entrypoint;
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/* Sanity check the cluster level */
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assert(cluster_node->level == MPIDR_AFFLVL1);
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/*
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* Keep the physical state of this cluster handy to decide
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* what action needs to be taken
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*/
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plat_state = psci_get_aff_phys_state(cluster_node);
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/*
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* Arch. management: Flush all levels of caches to PoC if the
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* cluster is to be shutdown
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*/
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if (plat_state == PSCI_STATE_OFF)
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dcsw_op_all(DCCISW);
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/*
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* Plat. Management. Allow the platform to do its cluster
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* specific bookeeping e.g. turn off interconnect coherency,
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* program the power controller etc.
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*/
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if (psci_plat_pm_ops->affinst_suspend) {
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/*
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* Sending the psci entrypoint is currently redundant
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* beyond affinity level 0 but one never knows what a
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* platform might do. Also it allows us to keep the
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* platform handler prototype the same.
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*/
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psci_entrypoint = (unsigned long) psci_aff_suspend_finish_entry;
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rc = psci_plat_pm_ops->affinst_suspend(mpidr,
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psci_entrypoint,
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ns_entrypoint,
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cluster_node->level,
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plat_state);
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}
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return rc;
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}
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static int psci_afflvl2_suspend(unsigned long mpidr,
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aff_map_node *system_node,
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unsigned long ns_entrypoint,
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unsigned long context_id,
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unsigned int power_state)
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{
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int rc = PSCI_E_SUCCESS;
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unsigned int plat_state;
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unsigned long psci_entrypoint;
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/* Cannot go beyond this */
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assert(system_node->level == MPIDR_AFFLVL2);
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/*
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* Keep the physical state of the system handy to decide what
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* action needs to be taken
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*/
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plat_state = psci_get_aff_phys_state(system_node);
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/*
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* Plat. Management : Allow the platform to do its bookeeping
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* at this affinity level
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*/
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if (psci_plat_pm_ops->affinst_suspend) {
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/*
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* Sending the psci entrypoint is currently redundant
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* beyond affinity level 0 but one never knows what a
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* platform might do. Also it allows us to keep the
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* platform handler prototype the same.
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*/
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psci_entrypoint = (unsigned long) psci_aff_suspend_finish_entry;
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rc = psci_plat_pm_ops->affinst_suspend(mpidr,
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psci_entrypoint,
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ns_entrypoint,
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system_node->level,
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plat_state);
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}
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return rc;
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}
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static const afflvl_suspend_handler psci_afflvl_suspend_handlers[] = {
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psci_afflvl0_suspend,
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psci_afflvl1_suspend,
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psci_afflvl2_suspend,
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};
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/*******************************************************************************
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* This function takes an array of pointers to affinity instance nodes in the
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* topology tree and calls the suspend handler for the corresponding affinity
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* levels
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******************************************************************************/
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static int psci_call_suspend_handlers(mpidr_aff_map_nodes mpidr_nodes,
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int start_afflvl,
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int end_afflvl,
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unsigned long mpidr,
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unsigned long entrypoint,
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unsigned long context_id,
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unsigned int power_state)
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{
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int rc = PSCI_E_INVALID_PARAMS, level;
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aff_map_node *node;
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for (level = start_afflvl; level <= end_afflvl; level++) {
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node = mpidr_nodes[level];
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if (node == NULL)
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continue;
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/*
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* TODO: In case of an error should there be a way
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* of restoring what we might have torn down at
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* lower affinity levels.
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*/
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rc = psci_afflvl_suspend_handlers[level](mpidr,
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node,
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entrypoint,
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context_id,
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power_state);
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if (rc != PSCI_E_SUCCESS)
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break;
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}
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return rc;
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}
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/*******************************************************************************
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* Top level handler which is called when a cpu wants to suspend its execution.
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* It is assumed that along with turning the cpu off, higher affinity levels
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* until the target affinity level will be turned off as well. It traverses
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* through all the affinity levels performing generic, architectural, platform
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* setup and state management e.g. for a cluster that's to be suspended, it will
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* call the platform specific code which will disable coherency at the
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* interconnect level if the cpu is the last in the cluster. For a cpu it could
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* mean programming the power controller etc.
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*
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* The state of all the relevant affinity levels is changed prior to calling the
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* affinity level specific handlers as their actions would depend upon the state
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* the affinity level is about to enter.
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*
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* The affinity level specific handlers are called in ascending order i.e. from
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* the lowest to the highest affinity level implemented by the platform because
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* to turn off affinity level X it is neccesary to turn off affinity level X - 1
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* first.
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*
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* CAUTION: This function is called with coherent stacks so that coherency can
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* be turned off and caches can be flushed safely.
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******************************************************************************/
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int psci_afflvl_suspend(unsigned long mpidr,
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unsigned long entrypoint,
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unsigned long context_id,
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unsigned int power_state,
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int start_afflvl,
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int end_afflvl)
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{
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int rc = PSCI_E_SUCCESS;
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unsigned int prev_state;
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mpidr_aff_map_nodes mpidr_nodes;
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mpidr &= MPIDR_AFFINITY_MASK;
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/*
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* Collect the pointers to the nodes in the topology tree for
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* each affinity instance in the mpidr. If this function does
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* not return successfully then either the mpidr or the affinity
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* levels are incorrect.
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*/
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rc = psci_get_aff_map_nodes(mpidr,
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start_afflvl,
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end_afflvl,
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mpidr_nodes);
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if (rc != PSCI_E_SUCCESS)
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return rc;
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/*
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* This function acquires the lock corresponding to each affinity
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* level so that by the time all locks are taken, the system topology
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* is snapshot and state management can be done safely.
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*/
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psci_acquire_afflvl_locks(mpidr,
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start_afflvl,
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end_afflvl,
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mpidr_nodes);
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/*
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* Keep the old cpu state handy. It will be used to restore the
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* system to its original state in case something goes wrong
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*/
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prev_state = psci_get_state(mpidr_nodes[MPIDR_AFFLVL0]->state);
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/*
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* State management: Update the state of each affinity instance
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* between the start and end affinity levels
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*/
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psci_change_state(mpidr_nodes,
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start_afflvl,
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end_afflvl,
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PSCI_STATE_SUSPEND);
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/* Perform generic, architecture and platform specific handling */
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rc = psci_call_suspend_handlers(mpidr_nodes,
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start_afflvl,
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end_afflvl,
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mpidr,
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entrypoint,
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context_id,
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power_state);
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/*
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* If an error is returned by a handler then restore the cpu state
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* to its original value. If the cpu state is restored then that
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* should result in the state of the higher affinity levels to
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* get restored as well.
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* TODO: We are not undoing any architectural or platform specific
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* operations that might have completed before encountering the
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* error. The system might not be in a stable state.
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*/
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if (rc != PSCI_E_SUCCESS)
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psci_change_state(mpidr_nodes,
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start_afflvl,
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end_afflvl,
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prev_state);
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/*
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* Release the locks corresponding to each affinity level in the
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* reverse order to which they were acquired.
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*/
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psci_release_afflvl_locks(mpidr,
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start_afflvl,
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end_afflvl,
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mpidr_nodes);
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return rc;
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}
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/*******************************************************************************
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* The following functions finish an earlier affinity suspend request. They
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* are called by the common finisher routine in psci_common.c.
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******************************************************************************/
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static unsigned int psci_afflvl0_suspend_finish(unsigned long mpidr,
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aff_map_node *cpu_node)
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{
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unsigned int index, plat_state, state, rc = PSCI_E_SUCCESS;
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assert(cpu_node->level == MPIDR_AFFLVL0);
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/* Ensure we have been woken up from a suspended state */
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state = psci_get_state(cpu_node->state);
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assert(state == PSCI_STATE_SUSPEND);
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/*
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* Plat. management: Perform the platform specific actions
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* before we change the state of the cpu e.g. enabling the
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* gic or zeroing the mailbox register. If anything goes
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* wrong then assert as there is no way to recover from this
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* situation.
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*/
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if (psci_plat_pm_ops->affinst_suspend_finish) {
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/* Get the physical state of this cpu */
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plat_state = psci_get_phys_state(state);
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rc = psci_plat_pm_ops->affinst_suspend_finish(mpidr,
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cpu_node->level,
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plat_state);
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assert(rc == PSCI_E_SUCCESS);
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}
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/* Get the index for restoring the re-entry information */
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index = cpu_node->data;
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/*
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* Arch. management: Restore the stashed secure architectural
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* context in the right order.
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*/
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write_vbar(psci_secure_context[index].vbar);
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write_daif(read_daif() | psci_secure_context[index].pstate);
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write_mair(psci_secure_context[index].mair);
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write_tcr(psci_secure_context[index].tcr);
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write_ttbr0(psci_secure_context[index].ttbr);
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write_sctlr(psci_secure_context[index].sctlr);
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/* MMU and coherency should be enabled by now */
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write_scr(psci_secure_context[index].scr);
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write_cptr(psci_secure_context[index].cptr);
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write_cpacr(psci_secure_context[index].cpacr);
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write_cntfrq_el0(psci_secure_context[index].cntfrq);
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/*
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* Generic management: Now we just need to retrieve the
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* information that we had stashed away during the suspend
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* call to set this cpu on its way.
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*/
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psci_get_ns_entry_info(index);
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/* Clean caches before re-entering normal world */
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dcsw_op_louis(DCCSW);
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return rc;
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}
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static unsigned int psci_afflvl1_suspend_finish(unsigned long mpidr,
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aff_map_node *cluster_node)
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{
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unsigned int plat_state, rc = PSCI_E_SUCCESS;
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assert(cluster_node->level == MPIDR_AFFLVL1);
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/*
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* Plat. management: Perform the platform specific actions
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* as per the old state of the cluster e.g. enabling
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* coherency at the interconnect depends upon the state with
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* which this cluster was powered up. If anything goes wrong
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* then assert as there is no way to recover from this
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* situation.
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*/
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if (psci_plat_pm_ops->affinst_suspend_finish) {
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/* Get the physical state of this cpu */
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plat_state = psci_get_aff_phys_state(cluster_node);
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rc = psci_plat_pm_ops->affinst_suspend_finish(mpidr,
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cluster_node->level,
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plat_state);
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assert(rc == PSCI_E_SUCCESS);
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}
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return rc;
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}
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static unsigned int psci_afflvl2_suspend_finish(unsigned long mpidr,
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aff_map_node *system_node)
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{
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unsigned int plat_state, rc = PSCI_E_SUCCESS;;
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/* Cannot go beyond this affinity level */
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assert(system_node->level == MPIDR_AFFLVL2);
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/*
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* Currently, there are no architectural actions to perform
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* at the system level.
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*/
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/*
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* Plat. management: Perform the platform specific actions
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* as per the old state of the cluster e.g. enabling
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* coherency at the interconnect depends upon the state with
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* which this cluster was powered up. If anything goes wrong
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* then assert as there is no way to recover from this
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* situation.
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*/
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if (psci_plat_pm_ops->affinst_suspend_finish) {
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/* Get the physical state of the system */
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plat_state = psci_get_aff_phys_state(system_node);
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rc = psci_plat_pm_ops->affinst_suspend_finish(mpidr,
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system_node->level,
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plat_state);
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assert(rc == PSCI_E_SUCCESS);
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}
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return rc;
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}
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const afflvl_power_on_finisher psci_afflvl_suspend_finishers[] = {
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psci_afflvl0_suspend_finish,
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psci_afflvl1_suspend_finish,
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psci_afflvl2_suspend_finish,
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};
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