618 lines
21 KiB
C
618 lines
21 KiB
C
/*
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* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <stdio.h>
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#include <string.h>
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#include <assert.h>
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#include <arch_helpers.h>
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#include <console.h>
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#include <platform.h>
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#include <psci.h>
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#include <psci_private.h>
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#include <runtime_svc.h>
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/*******************************************************************************
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* Arrays that contains information needs to resume a cpu's execution when woken
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* out of suspend or off states. 'psci_ns_einfo_idx' keeps track of the next
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* free index in the 'psci_ns_entry_info' & 'psci_secure_context' arrays. Each
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* cpu is allocated a single entry in each array during startup.
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******************************************************************************/
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secure_context psci_secure_context[PSCI_NUM_AFFS];
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ns_entry_info psci_ns_entry_info[PSCI_NUM_AFFS];
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unsigned int psci_ns_einfo_idx;
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/*******************************************************************************
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* Grand array that holds the platform's topology information for state
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* management of affinity instances. Each node (aff_map_node) in the array
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* corresponds to an affinity instance e.g. cluster, cpu within an mpidr
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******************************************************************************/
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aff_map_node psci_aff_map[PSCI_NUM_AFFS]
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__attribute__ ((section("tzfw_coherent_mem")));
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/*******************************************************************************
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* In a system, a certain number of affinity instances are present at an
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* affinity level. The cumulative number of instances across all levels are
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* stored in 'psci_aff_map'. The topology tree has been flattenned into this
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* array. To retrieve nodes, information about the extents of each affinity
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* level i.e. start index and end index needs to be present. 'psci_aff_limits'
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* stores this information.
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******************************************************************************/
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aff_limits_node psci_aff_limits[MPIDR_MAX_AFFLVL + 1];
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/*******************************************************************************
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* Pointer to functions exported by the platform to complete power mgmt. ops
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******************************************************************************/
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plat_pm_ops *psci_plat_pm_ops;
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/*******************************************************************************
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* Simple routine to retrieve the maximum affinity level supported by the
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* platform and check that it makes sense.
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******************************************************************************/
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int get_max_afflvl()
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{
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int aff_lvl;
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aff_lvl = plat_get_max_afflvl();
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assert(aff_lvl <= MPIDR_MAX_AFFLVL && aff_lvl >= MPIDR_AFFLVL0);
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return aff_lvl;
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}
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/*******************************************************************************
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* Simple routine to set the id of an affinity instance at a given level in the
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* mpidr.
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******************************************************************************/
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unsigned long mpidr_set_aff_inst(unsigned long mpidr,
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unsigned char aff_inst,
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int aff_lvl)
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{
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unsigned long aff_shift;
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assert(aff_lvl <= MPIDR_AFFLVL3);
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/*
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* Decide the number of bits to shift by depending upon
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* the affinity level
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*/
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aff_shift = get_afflvl_shift(aff_lvl);
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/* Clear the existing affinity instance & set the new one*/
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mpidr &= ~(MPIDR_AFFLVL_MASK << aff_shift);
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mpidr |= aff_inst << aff_shift;
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return mpidr;
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}
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/*******************************************************************************
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* This function sanity checks a range of affinity levels.
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******************************************************************************/
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int psci_check_afflvl_range(int start_afflvl, int end_afflvl)
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{
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/* Sanity check the parameters passed */
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if (end_afflvl > MPIDR_MAX_AFFLVL)
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return PSCI_E_INVALID_PARAMS;
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if (start_afflvl < MPIDR_AFFLVL0)
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return PSCI_E_INVALID_PARAMS;
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if (end_afflvl < start_afflvl)
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return PSCI_E_INVALID_PARAMS;
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return PSCI_E_SUCCESS;
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}
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/*******************************************************************************
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* This function is passed an array of pointers to affinity level nodes in the
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* topology tree for an mpidr. It picks up locks for each affinity level bottom
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* up in the range specified.
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******************************************************************************/
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void psci_acquire_afflvl_locks(unsigned long mpidr,
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int start_afflvl,
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int end_afflvl,
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mpidr_aff_map_nodes mpidr_nodes)
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{
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int level;
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for (level = start_afflvl; level <= end_afflvl; level++) {
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if (mpidr_nodes[level] == NULL)
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continue;
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bakery_lock_get(mpidr, &mpidr_nodes[level]->lock);
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}
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}
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/*******************************************************************************
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* This function is passed an array of pointers to affinity level nodes in the
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* topology tree for an mpidr. It releases the lock for each affinity level top
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* down in the range specified.
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******************************************************************************/
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void psci_release_afflvl_locks(unsigned long mpidr,
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int start_afflvl,
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int end_afflvl,
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mpidr_aff_map_nodes mpidr_nodes)
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{
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int level;
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for (level = end_afflvl; level >= start_afflvl; level--) {
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if (mpidr_nodes[level] == NULL)
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continue;
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bakery_lock_release(mpidr, &mpidr_nodes[level]->lock);
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}
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}
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/*******************************************************************************
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* Simple routine to determine whether an affinity instance at a given level
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* in an mpidr exists or not.
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******************************************************************************/
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int psci_validate_mpidr(unsigned long mpidr, int level)
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{
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aff_map_node *node;
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node = psci_get_aff_map_node(mpidr, level);
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if (node && (node->state & PSCI_AFF_PRESENT))
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return PSCI_E_SUCCESS;
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else
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return PSCI_E_INVALID_PARAMS;
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}
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/*******************************************************************************
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* Simple routine to determine the first affinity level instance that is present
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* between the start and end affinity levels. This helps to skip handling of
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* absent affinity levels while performing psci operations.
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* The start level can be > or <= to the end level depending upon whether this
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* routine is expected to search top down or bottom up.
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******************************************************************************/
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int psci_get_first_present_afflvl(unsigned long mpidr,
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int start_afflvl,
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int end_afflvl,
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aff_map_node **node)
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{
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int level;
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/* Check whether we have to search up or down */
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if (start_afflvl <= end_afflvl) {
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for (level = start_afflvl; level <= end_afflvl; level++) {
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*node = psci_get_aff_map_node(mpidr, level);
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if (*node && ((*node)->state & PSCI_AFF_PRESENT))
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break;
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}
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} else {
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for (level = start_afflvl; level >= end_afflvl; level--) {
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*node = psci_get_aff_map_node(mpidr, level);
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if (*node && ((*node)->state & PSCI_AFF_PRESENT))
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break;
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}
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}
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return level;
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}
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/*******************************************************************************
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* Iteratively change the affinity state between the current and target affinity
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* levels. The target state matters only if we are starting from affinity level
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* 0 i.e. a cpu otherwise the state depends upon the state of the lower affinity
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* levels.
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******************************************************************************/
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int psci_change_state(mpidr_aff_map_nodes mpidr_nodes,
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int start_afflvl,
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int end_afflvl,
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unsigned int tgt_state)
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{
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int rc = PSCI_E_SUCCESS, level;
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unsigned int state;
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aff_map_node *node;
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/*
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* Get a temp pointer to the node. It is not possible that affinity
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* level 0 is missing. Simply ignore higher missing levels.
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*/
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for (level = start_afflvl; level <= end_afflvl; level++) {
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node = mpidr_nodes[level];
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if (level == MPIDR_AFFLVL0) {
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assert(node);
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psci_set_state(node->state, tgt_state);
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} else {
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if (node == NULL)
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continue;
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state = psci_calculate_affinity_state(node);
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psci_set_state(node->state, state);
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}
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}
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/* If all went well then the cpu should be in the target state */
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if (start_afflvl == MPIDR_AFFLVL0) {
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node = mpidr_nodes[MPIDR_AFFLVL0];
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state = psci_get_state(node->state);
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assert(tgt_state == state);
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}
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return rc;
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}
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/*******************************************************************************
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* This routine does the heavy lifting for psci_change_state(). It examines the
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* state of each affinity instance at the next lower affinity level and decides
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* its final state accordingly. If a lower affinity instance is ON then the
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* higher affinity instance is ON. If all the lower affinity instances are OFF
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* then the higher affinity instance is OFF. If atleast one lower affinity
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* instance is SUSPENDED then the higher affinity instance is SUSPENDED. If only
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* a single lower affinity instance is ON_PENDING then the higher affinity
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* instance in ON_PENDING as well.
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******************************************************************************/
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unsigned int psci_calculate_affinity_state(aff_map_node *aff_node)
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{
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int ctr;
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unsigned int aff_count, hi_aff_state;
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unsigned long tempidr;
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aff_map_node *lo_aff_node;
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/* Cannot calculate lowest affinity state. It is simply assigned */
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assert(aff_node->level > MPIDR_AFFLVL0);
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/*
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* Find the number of affinity instances at level X-1 e.g. number of
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* cpus in a cluster. The level X state depends upon the state of each
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* instance at level X-1
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*/
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hi_aff_state = PSCI_STATE_OFF;
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aff_count = plat_get_aff_count(aff_node->level - 1, aff_node->mpidr);
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for (ctr = 0; ctr < aff_count; ctr++) {
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/*
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* Create a mpidr for each lower affinity level (X-1). Use their
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* states to influence the higher affinity state (X).
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*/
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tempidr = mpidr_set_aff_inst(aff_node->mpidr,
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ctr,
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aff_node->level - 1);
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lo_aff_node = psci_get_aff_map_node(tempidr,
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aff_node->level - 1);
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assert(lo_aff_node);
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/* Continue only if the cpu exists within the cluster */
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if (!(lo_aff_node->state & PSCI_AFF_PRESENT))
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continue;
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switch (psci_get_state(lo_aff_node->state)) {
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/*
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* If any lower affinity is on within the cluster, then
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* the higher affinity is on.
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*/
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case PSCI_STATE_ON:
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return PSCI_STATE_ON;
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/*
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* At least one X-1 needs to be suspended for X to be suspended
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* but it is effectively on for the affinity_info call.
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* SUSPEND > ON_PENDING > OFF.
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*/
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case PSCI_STATE_SUSPEND:
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hi_aff_state = PSCI_STATE_SUSPEND;
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continue;
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/*
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* Atleast one X-1 needs to be on_pending & the rest off for X
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* to be on_pending. ON_PENDING > OFF.
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*/
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case PSCI_STATE_ON_PENDING:
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if (hi_aff_state != PSCI_STATE_SUSPEND)
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hi_aff_state = PSCI_STATE_ON_PENDING;
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continue;
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/* Higher affinity is off if all lower affinities are off. */
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case PSCI_STATE_OFF:
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continue;
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default:
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assert(0);
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}
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}
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return hi_aff_state;
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}
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/*******************************************************************************
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* This function retrieves all the stashed information needed to correctly
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* resume a cpu's execution in the non-secure state after it has been physically
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* powered on i.e. turned ON or resumed from SUSPEND
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******************************************************************************/
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void psci_get_ns_entry_info(unsigned int index)
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{
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unsigned long sctlr = 0, scr, el_status, id_aa64pfr0;
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gp_regs *ns_gp_regs;
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scr = read_scr();
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/* Switch to the non-secure view of the registers */
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write_scr(scr | SCR_NS_BIT);
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/* Find out which EL we are going to */
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id_aa64pfr0 = read_id_aa64pfr0_el1();
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el_status = (id_aa64pfr0 >> ID_AA64PFR0_EL2_SHIFT) &
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ID_AA64PFR0_ELX_MASK;
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/* Restore endianess */
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if (psci_ns_entry_info[index].sctlr & SCTLR_EE_BIT)
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sctlr |= SCTLR_EE_BIT;
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else
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sctlr &= ~SCTLR_EE_BIT;
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/* Turn off MMU and Caching */
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sctlr &= ~(SCTLR_M_BIT | SCTLR_C_BIT | SCTLR_M_BIT);
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/* Set the register width */
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if (psci_ns_entry_info[index].scr & SCR_RW_BIT)
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scr |= SCR_RW_BIT;
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else
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scr &= ~SCR_RW_BIT;
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scr |= SCR_NS_BIT;
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if (el_status)
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write_sctlr_el2(sctlr);
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else
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write_sctlr_el1(sctlr);
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/* Fulfill the cpu_on entry reqs. as per the psci spec */
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write_scr(scr);
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write_elr(psci_ns_entry_info[index].eret_info.entrypoint);
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/*
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* Set the general purpose registers to ~0 upon entry into the
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* non-secure world except for x0 which should contain the
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* context id & spsr. This is done directly on the "would be"
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* stack pointer. Prior to entry into the non-secure world, an
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* offset equivalent to the size of the 'gp_regs' structure is
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* added to the sp. This general purpose register context is
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* retrieved then.
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*/
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ns_gp_regs = (gp_regs *) platform_get_stack(read_mpidr());
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ns_gp_regs--;
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memset(ns_gp_regs, ~0, sizeof(*ns_gp_regs));
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ns_gp_regs->x0 = psci_ns_entry_info[index].context_id;
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ns_gp_regs->spsr = psci_ns_entry_info[index].eret_info.spsr;
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}
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/*******************************************************************************
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* This function retrieves and stashes all the information needed to correctly
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* resume a cpu's execution in the non-secure state after it has been physically
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* powered on i.e. turned ON or resumed from SUSPEND. This is done prior to
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* turning it on or before suspending it.
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******************************************************************************/
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int psci_set_ns_entry_info(unsigned int index,
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unsigned long entrypoint,
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unsigned long context_id)
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{
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int rc = PSCI_E_SUCCESS;
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unsigned int rw, mode, ee, spsr = 0;
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unsigned long id_aa64pfr0 = read_id_aa64pfr0_el1(), scr = read_scr();
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unsigned long el_status;
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/* Figure out what mode do we enter the non-secure world in */
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el_status = (id_aa64pfr0 >> ID_AA64PFR0_EL2_SHIFT) &
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ID_AA64PFR0_ELX_MASK;
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/*
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* Figure out whether the cpu enters the non-secure address space
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* in aarch32 or aarch64
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*/
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rw = scr & SCR_RW_BIT;
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if (rw) {
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/*
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* Check whether a Thumb entry point has been provided for an
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* aarch64 EL
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*/
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if (entrypoint & 0x1)
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return PSCI_E_INVALID_PARAMS;
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if (el_status && (scr & SCR_HCE_BIT)) {
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mode = MODE_EL2;
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ee = read_sctlr_el2() & SCTLR_EE_BIT;
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} else {
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mode = MODE_EL1;
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ee = read_sctlr_el1() & SCTLR_EE_BIT;
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}
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spsr = DAIF_DBG_BIT | DAIF_ABT_BIT;
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spsr |= DAIF_IRQ_BIT | DAIF_FIQ_BIT;
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spsr <<= PSR_DAIF_SHIFT;
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spsr |= make_spsr(mode, MODE_SP_ELX, !rw);
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psci_ns_entry_info[index].sctlr |= ee;
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psci_ns_entry_info[index].scr |= SCR_RW_BIT;
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} else {
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/* Check whether aarch32 has to be entered in Thumb mode */
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if (entrypoint & 0x1)
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spsr = SPSR32_T_BIT;
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if (el_status && (scr & SCR_HCE_BIT)) {
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mode = AARCH32_MODE_HYP;
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ee = read_sctlr_el2() & SCTLR_EE_BIT;
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} else {
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mode = AARCH32_MODE_SVC;
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ee = read_sctlr_el1() & SCTLR_EE_BIT;
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}
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/*
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* TODO: Choose async. exception bits if HYP mode is not
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* implemented according to the values of SCR.{AW, FW} bits
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*/
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spsr |= DAIF_ABT_BIT | DAIF_IRQ_BIT | DAIF_FIQ_BIT;
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spsr <<= PSR_DAIF_SHIFT;
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if(ee)
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spsr |= SPSR32_EE_BIT;
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spsr |= mode;
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/* Ensure that the CSPR.E and SCTLR.EE bits match */
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psci_ns_entry_info[index].sctlr |= ee;
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psci_ns_entry_info[index].scr &= ~SCR_RW_BIT;
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}
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psci_ns_entry_info[index].eret_info.entrypoint = entrypoint;
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psci_ns_entry_info[index].eret_info.spsr = spsr;
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psci_ns_entry_info[index].context_id = context_id;
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return rc;
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}
|
|
|
|
/*******************************************************************************
|
|
* An affinity level could be on, on_pending, suspended or off. These are the
|
|
* logical states it can be in. Physically either it is off or on. When it is in
|
|
* the state on_pending then it is about to be turned on. It is not possible to
|
|
* tell whether that's actually happenned or not. So we err on the side of
|
|
* caution & treat the affinity level as being turned off.
|
|
******************************************************************************/
|
|
inline unsigned int psci_get_phys_state(unsigned int aff_state)
|
|
{
|
|
return (aff_state != PSCI_STATE_ON ? PSCI_STATE_OFF : PSCI_STATE_ON);
|
|
}
|
|
|
|
unsigned int psci_get_aff_phys_state(aff_map_node *aff_node)
|
|
{
|
|
unsigned int aff_state;
|
|
|
|
aff_state = psci_get_state(aff_node->state);
|
|
return psci_get_phys_state(aff_state);
|
|
}
|
|
|
|
/*******************************************************************************
|
|
* This function takes an array of pointers to affinity instance nodes in the
|
|
* topology tree and calls the physical power on handler for the corresponding
|
|
* affinity levels
|
|
******************************************************************************/
|
|
static int psci_call_power_on_handlers(mpidr_aff_map_nodes mpidr_nodes,
|
|
int start_afflvl,
|
|
int end_afflvl,
|
|
afflvl_power_on_finisher *pon_handlers,
|
|
unsigned long mpidr)
|
|
{
|
|
int rc = PSCI_E_INVALID_PARAMS, level;
|
|
aff_map_node *node;
|
|
|
|
for (level = end_afflvl; level >= start_afflvl; level--) {
|
|
node = mpidr_nodes[level];
|
|
if (node == NULL)
|
|
continue;
|
|
|
|
/*
|
|
* If we run into any trouble while powering up an
|
|
* affinity instance, then there is no recovery path
|
|
* so simply return an error and let the caller take
|
|
* care of the situation.
|
|
*/
|
|
rc = pon_handlers[level](mpidr, node);
|
|
if (rc != PSCI_E_SUCCESS)
|
|
break;
|
|
}
|
|
|
|
return rc;
|
|
}
|
|
|
|
/*******************************************************************************
|
|
* Generic handler which is called when a cpu is physically powered on. It
|
|
* traverses through all the affinity levels performing generic, architectural,
|
|
* platform setup and state management e.g. for a cluster that's been powered
|
|
* on, it will call the platform specific code which will enable coherency at
|
|
* the interconnect level. For a cpu it could mean turning on the MMU etc.
|
|
*
|
|
* The state of all the relevant affinity levels is changed after calling the
|
|
* affinity level specific handlers as their actions would depend upon the state
|
|
* the affinity level is exiting from.
|
|
*
|
|
* The affinity level specific handlers are called in descending order i.e. from
|
|
* the highest to the lowest affinity level implemented by the platform because
|
|
* to turn on affinity level X it is neccesary to turn on affinity level X + 1
|
|
* first.
|
|
*
|
|
* CAUTION: This function is called with coherent stacks so that coherency and
|
|
* the mmu can be turned on safely.
|
|
******************************************************************************/
|
|
void psci_afflvl_power_on_finish(unsigned long mpidr,
|
|
int start_afflvl,
|
|
int end_afflvl,
|
|
afflvl_power_on_finisher *pon_handlers)
|
|
{
|
|
mpidr_aff_map_nodes mpidr_nodes;
|
|
int rc;
|
|
|
|
mpidr &= MPIDR_AFFINITY_MASK;;
|
|
|
|
/*
|
|
* Collect the pointers to the nodes in the topology tree for
|
|
* each affinity instance in the mpidr. If this function does
|
|
* not return successfully then either the mpidr or the affinity
|
|
* levels are incorrect. Either case is an irrecoverable error.
|
|
*/
|
|
rc = psci_get_aff_map_nodes(mpidr,
|
|
start_afflvl,
|
|
end_afflvl,
|
|
mpidr_nodes);
|
|
assert (rc == PSCI_E_SUCCESS);
|
|
|
|
/*
|
|
* This function acquires the lock corresponding to each affinity
|
|
* level so that by the time all locks are taken, the system topology
|
|
* is snapshot and state management can be done safely.
|
|
*/
|
|
psci_acquire_afflvl_locks(mpidr,
|
|
start_afflvl,
|
|
end_afflvl,
|
|
mpidr_nodes);
|
|
|
|
/* Perform generic, architecture and platform specific handling */
|
|
rc = psci_call_power_on_handlers(mpidr_nodes,
|
|
start_afflvl,
|
|
end_afflvl,
|
|
pon_handlers,
|
|
mpidr);
|
|
assert (rc == PSCI_E_SUCCESS);
|
|
|
|
/*
|
|
* State management: Update the state of each affinity instance
|
|
* between the start and end affinity levels
|
|
*/
|
|
psci_change_state(mpidr_nodes,
|
|
start_afflvl,
|
|
end_afflvl,
|
|
PSCI_STATE_ON);
|
|
|
|
/*
|
|
* This loop releases the lock corresponding to each affinity level
|
|
* in the reverse order to which they were acquired.
|
|
*/
|
|
psci_release_afflvl_locks(mpidr,
|
|
start_afflvl,
|
|
end_afflvl,
|
|
mpidr_nodes);
|
|
}
|