73 lines
2.8 KiB
C
73 lines
2.8 KiB
C
/*
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* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __CCI_400_H__
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#define __CCI_400_H__
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/* Slave interface offsets from PERIPHBASE */
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#define SLAVE_IFACE4_OFFSET 0x5000
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#define SLAVE_IFACE3_OFFSET 0x4000
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#define SLAVE_IFACE2_OFFSET 0x3000
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#define SLAVE_IFACE1_OFFSET 0x2000
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#define SLAVE_IFACE0_OFFSET 0x1000
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#define SLAVE_IFACE_OFFSET(index) SLAVE_IFACE0_OFFSET + (0x1000 * index)
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/* Control and ID register offsets */
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#define CTRL_OVERRIDE_REG 0x0
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#define SPEC_CTRL_REG 0x4
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#define SECURE_ACCESS_REG 0x8
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#define STATUS_REG 0xc
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#define IMPRECISE_ERR_REG 0x10
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#define PERFMON_CTRL_REG 0x100
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/* Slave interface register offsets */
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#define SNOOP_CTRL_REG 0x0
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#define SH_OVERRIDE_REG 0x4
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#define READ_CHNL_QOS_VAL_OVERRIDE_REG 0x100
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#define WRITE_CHNL_QOS_VAL_OVERRIDE_REG 0x104
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#define QOS_CTRL_REG 0x10c
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#define MAX_OT_REG 0x110
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#define TARGET_LATENCY_REG 0x130
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#define LATENCY_REGULATION_REG 0x134
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#define QOS_RANGE_REG 0x138
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/* Snoop Control register bit definitions */
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#define DVM_EN_BIT (1 << 1)
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#define SNOOP_EN_BIT (1 << 0)
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/* Status register bit definitions */
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#define CHANGE_PENDING_BIT (1 << 0)
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/* Function declarations */
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extern void cci_enable_coherency(unsigned long mpidr);
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extern void cci_disable_coherency(unsigned long mpidr);
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#endif /* __CCI_400_H__ */
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