596 lines
20 KiB
C
596 lines
20 KiB
C
/*
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* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <string.h>
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#include <assert.h>
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#include <arch_helpers.h>
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#include <platform.h>
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#include <bl_common.h>
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/* Included only for error codes */
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#include <psci.h>
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unsigned char platform_normal_stacks[PLATFORM_STACK_SIZE][PLATFORM_CORE_COUNT]
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__attribute__ ((aligned(PLATFORM_CACHE_LINE_SIZE),
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section("tzfw_normal_stacks")));
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/*******************************************************************************
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* This array holds the characteristics of the differences between the three
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* FVP platforms (Base, A53_A57 & Foundation). It will be populated during cold
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* boot at each boot stage by the primary before enabling the MMU (to allow cci
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* configuration) & used thereafter. Each BL will have its own copy to allow
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* independent operation.
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******************************************************************************/
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static unsigned long platform_config[CONFIG_LIMIT];
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/*******************************************************************************
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* TODO: Check page table alignment to avoid space wastage
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******************************************************************************/
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/*******************************************************************************
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* Level 1 translation tables need 4 entries for the 4GB address space accessib-
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* le by the secure firmware. Input address space will be restricted using the
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* T0SZ settings in the TCR.
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******************************************************************************/
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static unsigned long l1_xlation_table[ADDR_SPACE_SIZE >> 30]
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__attribute__ ((aligned((ADDR_SPACE_SIZE >> 30) << 3)));
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/*******************************************************************************
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* Level 2 translation tables describe the first & second gb of the address
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* space needed to address secure peripherals e.g. trusted ROM and RAM.
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******************************************************************************/
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static unsigned long l2_xlation_table[NUM_L2_PAGETABLES][NUM_2MB_IN_GB]
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__attribute__ ((aligned(NUM_2MB_IN_GB << 3)));
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/*******************************************************************************
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* Level 3 translation tables (2 sets) describe the trusted & non-trusted RAM
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* regions at a granularity of 4K.
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******************************************************************************/
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static unsigned long l3_xlation_table[NUM_L3_PAGETABLES][NUM_4K_IN_2MB]
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__attribute__ ((aligned(NUM_4K_IN_2MB << 3)));
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/*******************************************************************************
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* Helper to create a level 1/2 table descriptor which points to a level 2/3
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* table.
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******************************************************************************/
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static unsigned long create_table_desc(unsigned long *next_table_ptr)
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{
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unsigned long desc = (unsigned long) next_table_ptr;
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/* Clear the last 12 bits */
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desc >>= FOUR_KB_SHIFT;
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desc <<= FOUR_KB_SHIFT;
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desc |= TABLE_DESC;
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return desc;
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}
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/*******************************************************************************
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* Helper to create a level 1/2/3 block descriptor which maps the va to addr
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******************************************************************************/
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static unsigned long create_block_desc(unsigned long desc,
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unsigned long addr,
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unsigned int level)
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{
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switch (level) {
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case LEVEL1:
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desc |= (addr << FIRST_LEVEL_DESC_N) | BLOCK_DESC;
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break;
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case LEVEL2:
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desc |= (addr << SECOND_LEVEL_DESC_N) | BLOCK_DESC;
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break;
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case LEVEL3:
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desc |= (addr << THIRD_LEVEL_DESC_N) | TABLE_DESC;
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break;
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default:
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assert(0);
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}
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return desc;
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}
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/*******************************************************************************
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* Helper to create a level 1/2/3 block descriptor which maps the va to output_
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* addr with Device nGnRE attributes.
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******************************************************************************/
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static unsigned long create_device_block(unsigned long output_addr,
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unsigned int level,
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unsigned int ns)
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{
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unsigned long upper_attrs, lower_attrs, desc;
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lower_attrs = LOWER_ATTRS(ACCESS_FLAG | OSH | AP_RW);
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lower_attrs |= LOWER_ATTRS(ns | ATTR_DEVICE_INDEX);
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upper_attrs = UPPER_ATTRS(XN);
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desc = upper_attrs | lower_attrs;
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return create_block_desc(desc, output_addr, level);
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}
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/*******************************************************************************
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* Helper to create a level 1/2/3 block descriptor which maps the va to output_
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* addr with inner-shareable normal wbwa read-only memory attributes.
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******************************************************************************/
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static unsigned long create_romem_block(unsigned long output_addr,
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unsigned int level,
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unsigned int ns)
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{
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unsigned long upper_attrs, lower_attrs, desc;
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lower_attrs = LOWER_ATTRS(ACCESS_FLAG | ISH | AP_RO);
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lower_attrs |= LOWER_ATTRS(ns | ATTR_IWBWA_OWBWA_NTR_INDEX);
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upper_attrs = UPPER_ATTRS(0ull);
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desc = upper_attrs | lower_attrs;
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return create_block_desc(desc, output_addr, level);
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}
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/*******************************************************************************
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* Helper to create a level 1/2/3 block descriptor which maps the va to output_
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* addr with inner-shareable normal wbwa read-write memory attributes.
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******************************************************************************/
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static unsigned long create_rwmem_block(unsigned long output_addr,
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unsigned int level,
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unsigned int ns)
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{
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unsigned long upper_attrs, lower_attrs, desc;
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lower_attrs = LOWER_ATTRS(ACCESS_FLAG | ISH | AP_RW);
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lower_attrs |= LOWER_ATTRS(ns | ATTR_IWBWA_OWBWA_NTR_INDEX);
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upper_attrs = UPPER_ATTRS(XN);
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desc = upper_attrs | lower_attrs;
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return create_block_desc(desc, output_addr, level);
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}
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/*******************************************************************************
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* Create page tables as per the platform memory map. Certain aspects of page
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* talble creating have been abstracted in the above routines. This can be impr-
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* oved further.
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* TODO: Move the page table setup helpers into the arch or lib directory
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*******************************************************************************/
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static unsigned long fill_xlation_tables(meminfo *tzram_layout,
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unsigned long ro_start,
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unsigned long ro_limit,
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unsigned long coh_start,
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unsigned long coh_limit)
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{
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unsigned long l2_desc, l3_desc;
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unsigned long *xt_addr = 0, *pt_addr, off = 0;
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unsigned long trom_start_index, trom_end_index;
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unsigned long tzram_start_index, tzram_end_index;
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unsigned long flash0_start_index, flash0_end_index;
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unsigned long flash1_start_index, flash1_end_index;
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unsigned long vram_start_index, vram_end_index;
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unsigned long nsram_start_index, nsram_end_index;
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unsigned long tdram_start_index, tdram_end_index;
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unsigned long dram_start_index, dram_end_index;
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unsigned long dev0_start_index, dev0_end_index;
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unsigned long dev1_start_index, dev1_end_index;
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unsigned int idx;
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/*****************************************************************
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* LEVEL1 PAGETABLE SETUP
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*
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* Find the start and end indices of the memory peripherals in the
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* first level pagetables. These are the main areas we care about.
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* Also bump the end index by one if its equal to the start to
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* allow for regions which lie completely in a GB.
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*****************************************************************/
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trom_start_index = ONE_GB_INDEX(TZROM_BASE);
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dev0_start_index = ONE_GB_INDEX(TZRNG_BASE);
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dram_start_index = ONE_GB_INDEX(DRAM_BASE);
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dram_end_index = ONE_GB_INDEX(DRAM_BASE + DRAM_SIZE);
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if (dram_end_index == dram_start_index)
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dram_end_index++;
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/*
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* Fill up the level1 translation table first
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*/
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for (idx = 0; idx < (ADDR_SPACE_SIZE >> 30); idx++) {
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/*
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* Fill up the entry for the TZROM. This will cover
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* everything in the first GB.
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*/
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if (idx == trom_start_index) {
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xt_addr = &l2_xlation_table[GB1_L2_PAGETABLE][0];
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l1_xlation_table[idx] = create_table_desc(xt_addr);
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continue;
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}
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/*
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* Mark the second gb as device
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*/
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if (idx == dev0_start_index) {
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xt_addr = &l2_xlation_table[GB2_L2_PAGETABLE][0];
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l1_xlation_table[idx] = create_table_desc(xt_addr);
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continue;
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}
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/*
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* Fill up the block entry for the DRAM with Normal
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* inner-WBWA outer-WBWA non-transient attributes.
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* This will cover 2-4GB. Note that the acesses are
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* marked as non-secure.
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*/
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if ((idx >= dram_start_index) && (idx < dram_end_index)) {
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l1_xlation_table[idx] = create_rwmem_block(idx, LEVEL1,
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NS);
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continue;
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}
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assert(0);
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}
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/*****************************************************************
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* LEVEL2 PAGETABLE SETUP
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*
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* Find the start and end indices of the memory & peripherals in the
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* second level pagetables.
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******************************************************************/
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/* Initializations for the 1st GB */
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trom_start_index = TWO_MB_INDEX(TZROM_BASE);
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trom_end_index = TWO_MB_INDEX(TZROM_BASE + TZROM_SIZE);
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if (trom_end_index == trom_start_index)
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trom_end_index++;
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tdram_start_index = TWO_MB_INDEX(TZDRAM_BASE);
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tdram_end_index = TWO_MB_INDEX(TZDRAM_BASE + TZDRAM_SIZE);
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if (tdram_end_index == tdram_start_index)
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tdram_end_index++;
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flash0_start_index = TWO_MB_INDEX(FLASH0_BASE);
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flash0_end_index = TWO_MB_INDEX(FLASH0_BASE + TZROM_SIZE);
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if (flash0_end_index == flash0_start_index)
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flash0_end_index++;
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flash1_start_index = TWO_MB_INDEX(FLASH1_BASE);
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flash1_end_index = TWO_MB_INDEX(FLASH1_BASE + FLASH1_SIZE);
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if (flash1_end_index == flash1_start_index)
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flash1_end_index++;
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vram_start_index = TWO_MB_INDEX(VRAM_BASE);
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vram_end_index = TWO_MB_INDEX(VRAM_BASE + VRAM_SIZE);
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if (vram_end_index == vram_start_index)
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vram_end_index++;
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dev0_start_index = TWO_MB_INDEX(DEVICE0_BASE);
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dev0_end_index = TWO_MB_INDEX(DEVICE0_BASE + DEVICE0_SIZE);
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if (dev0_end_index == dev0_start_index)
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dev0_end_index++;
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dev1_start_index = TWO_MB_INDEX(DEVICE1_BASE);
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dev1_end_index = TWO_MB_INDEX(DEVICE1_BASE + DEVICE1_SIZE);
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if (dev1_end_index == dev1_start_index)
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dev1_end_index++;
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/* Since the size is < 2M this is a single index */
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tzram_start_index = TWO_MB_INDEX(tzram_layout->total_base);
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nsram_start_index = TWO_MB_INDEX(NSRAM_BASE);
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/*
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* Fill up the level2 translation table for the first GB next
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*/
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for (idx = 0; idx < NUM_2MB_IN_GB; idx++) {
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l2_desc = INVALID_DESC;
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xt_addr = &l2_xlation_table[GB1_L2_PAGETABLE][idx];
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/* Block entries for 64M of trusted Boot ROM */
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if ((idx >= trom_start_index) && (idx < trom_end_index))
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l2_desc = create_romem_block(idx, LEVEL2, 0);
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/* Single L3 page table entry for 256K of TZRAM */
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if (idx == tzram_start_index) {
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pt_addr = &l3_xlation_table[TZRAM_PAGETABLE][0];
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l2_desc = create_table_desc(pt_addr);
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}
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/* Block entries for 32M of trusted DRAM */
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if ((idx >= tdram_start_index) && (idx <= tdram_end_index))
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l2_desc = create_rwmem_block(idx, LEVEL2, 0);
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/* Block entries for 64M of aliased trusted Boot ROM */
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if ((idx >= flash0_start_index) && (idx < flash0_end_index))
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l2_desc = create_romem_block(idx, LEVEL2, 0);
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/* Block entries for 64M of flash1 */
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if ((idx >= flash1_start_index) && (idx < flash1_end_index))
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l2_desc = create_romem_block(idx, LEVEL2, 0);
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/* Block entries for 32M of VRAM */
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if ((idx >= vram_start_index) && (idx < vram_end_index))
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l2_desc = create_rwmem_block(idx, LEVEL2, 0);
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/* Block entries for all the devices in the first gb */
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if ((idx >= dev0_start_index) && (idx < dev0_end_index))
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l2_desc = create_device_block(idx, LEVEL2, 0);
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/* Block entries for all the devices in the first gb */
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if ((idx >= dev1_start_index) && (idx < dev1_end_index))
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l2_desc = create_device_block(idx, LEVEL2, 0);
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/* Single L3 page table entry for 64K of NSRAM */
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if (idx == nsram_start_index) {
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pt_addr = &l3_xlation_table[NSRAM_PAGETABLE][0];
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l2_desc = create_table_desc(pt_addr);
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}
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*xt_addr = l2_desc;
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}
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/*
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* Initializations for the 2nd GB. Mark everything as device
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* for the time being as the memory map is not final. Each
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* index will need to be offset'ed to allow absolute values
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*/
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off = NUM_2MB_IN_GB;
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for (idx = off; idx < (NUM_2MB_IN_GB + off); idx++) {
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l2_desc = create_device_block(idx, LEVEL2, 0);
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xt_addr = &l2_xlation_table[GB2_L2_PAGETABLE][idx - off];
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*xt_addr = l2_desc;
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}
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/*****************************************************************
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* LEVEL3 PAGETABLE SETUP
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*****************************************************************/
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/* Fill up the level3 pagetable for the trusted SRAM. */
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tzram_start_index = FOUR_KB_INDEX(tzram_layout->total_base);
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tzram_end_index = FOUR_KB_INDEX(tzram_layout->total_base +
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tzram_layout->total_size);
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if (tzram_end_index == tzram_start_index)
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tzram_end_index++;
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/* Reusing trom* to mark RO memory. */
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trom_start_index = FOUR_KB_INDEX(ro_start);
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trom_end_index = FOUR_KB_INDEX(ro_limit);
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if (trom_end_index == trom_start_index)
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trom_end_index++;
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/* Reusing dev* to mark coherent device memory. */
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dev0_start_index = FOUR_KB_INDEX(coh_start);
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dev0_end_index = FOUR_KB_INDEX(coh_limit);
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if (dev0_end_index == dev0_start_index)
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dev0_end_index++;
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/* Each index will need to be offset'ed to allow absolute values */
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off = FOUR_KB_INDEX(TZRAM_BASE);
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for (idx = off; idx < (NUM_4K_IN_2MB + off); idx++) {
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l3_desc = INVALID_DESC;
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xt_addr = &l3_xlation_table[TZRAM_PAGETABLE][idx - off];
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if (idx >= tzram_start_index && idx < tzram_end_index)
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l3_desc = create_rwmem_block(idx, LEVEL3, 0);
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if (idx >= trom_start_index && idx < trom_end_index)
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l3_desc = create_romem_block(idx, LEVEL3, 0);
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if (idx >= dev0_start_index && idx < dev0_end_index)
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l3_desc = create_device_block(idx, LEVEL3, 0);
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*xt_addr = l3_desc;
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}
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/* Fill up the level3 pagetable for the non-trusted SRAM. */
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nsram_start_index = FOUR_KB_INDEX(NSRAM_BASE);
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nsram_end_index = FOUR_KB_INDEX(NSRAM_BASE + NSRAM_SIZE);
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if (nsram_end_index == nsram_start_index)
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nsram_end_index++;
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/* Each index will need to be offset'ed to allow absolute values */
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off = FOUR_KB_INDEX(NSRAM_BASE);
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for (idx = off; idx < (NUM_4K_IN_2MB + off); idx++) {
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l3_desc = INVALID_DESC;
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xt_addr = &l3_xlation_table[NSRAM_PAGETABLE][idx - off];
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if (idx >= nsram_start_index && idx < nsram_end_index)
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l3_desc = create_rwmem_block(idx, LEVEL3, NS);
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*xt_addr = l3_desc;
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}
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return (unsigned long) l1_xlation_table;
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}
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/*******************************************************************************
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* Enable the MMU assuming that the pagetables have already been created
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*******************************************************************************/
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void enable_mmu()
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{
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unsigned long mair, tcr, ttbr, sctlr;
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unsigned long current_el = read_current_el();
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/* Set the attributes in the right indices of the MAIR */
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mair = MAIR_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX);
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mair |= MAIR_ATTR_SET(ATTR_IWBWA_OWBWA_NTR,
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ATTR_IWBWA_OWBWA_NTR_INDEX);
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write_mair(mair);
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/*
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* Set TCR bits as well. Inner & outer WBWA & shareable + T0SZ = 32
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*/
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tcr = TCR_SH_INNER_SHAREABLE | TCR_RGN_OUTER_WBA |
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TCR_RGN_INNER_WBA | TCR_T0SZ_4GB;
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if (GET_EL(current_el) == MODE_EL3) {
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tcr |= TCR_EL3_RES1;
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/* Invalidate EL3 TLBs */
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tlbialle3();
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} else {
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/* Invalidate EL1 TLBs */
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tlbivmalle1();
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}
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write_tcr(tcr);
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/* Set TTBR bits as well */
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assert(((unsigned long)l1_xlation_table & (sizeof(l1_xlation_table) - 1)) == 0);
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ttbr = (unsigned long) l1_xlation_table;
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write_ttbr0(ttbr);
|
|
|
|
sctlr = read_sctlr();
|
|
sctlr |= SCTLR_WXN_BIT | SCTLR_M_BIT | SCTLR_I_BIT;
|
|
sctlr |= SCTLR_A_BIT | SCTLR_C_BIT;
|
|
write_sctlr(sctlr);
|
|
|
|
return;
|
|
}
|
|
|
|
void disable_mmu(void)
|
|
{
|
|
/* Zero out the MMU related registers */
|
|
write_mair(0);
|
|
write_tcr(0);
|
|
write_ttbr0(0);
|
|
write_sctlr(0);
|
|
|
|
/* Flush the caches */
|
|
dcsw_op_all(DCCISW);
|
|
|
|
return;
|
|
}
|
|
|
|
/*******************************************************************************
|
|
* Setup the pagetables as per the platform memory map & initialize the mmu
|
|
*******************************************************************************/
|
|
void configure_mmu(meminfo *mem_layout,
|
|
unsigned long ro_start,
|
|
unsigned long ro_limit,
|
|
unsigned long coh_start,
|
|
unsigned long coh_limit)
|
|
{
|
|
assert(IS_PAGE_ALIGNED(ro_start));
|
|
assert(IS_PAGE_ALIGNED(ro_limit));
|
|
assert(IS_PAGE_ALIGNED(coh_start));
|
|
assert(IS_PAGE_ALIGNED(coh_limit));
|
|
|
|
fill_xlation_tables(mem_layout,
|
|
ro_start,
|
|
ro_limit,
|
|
coh_start,
|
|
coh_limit);
|
|
enable_mmu();
|
|
return;
|
|
}
|
|
|
|
/* Simple routine which returns a configuration variable value */
|
|
unsigned long platform_get_cfgvar(unsigned int var_id)
|
|
{
|
|
assert(var_id < CONFIG_LIMIT);
|
|
return platform_config[var_id];
|
|
}
|
|
|
|
/*******************************************************************************
|
|
* A single boot loader stack is expected to work on both the Foundation FVP
|
|
* models and the two flavours of the Base FVP models (AEMv8 & Cortex). The
|
|
* SYS_ID register provides a mechanism for detecting the differences between
|
|
* these platforms. This information is stored in a per-BL array to allow the
|
|
* code to take the correct path.Per BL platform configuration.
|
|
******************************************************************************/
|
|
int platform_config_setup(void)
|
|
{
|
|
unsigned int rev, hbi, bld, arch, sys_id, midr_pn;
|
|
|
|
sys_id = mmio_read_32(VE_SYSREGS_BASE + V2M_SYS_ID);
|
|
rev = (sys_id >> SYS_ID_REV_SHIFT) & SYS_ID_REV_MASK;
|
|
hbi = (sys_id >> SYS_ID_HBI_SHIFT) & SYS_ID_HBI_MASK;
|
|
bld = (sys_id >> SYS_ID_BLD_SHIFT) & SYS_ID_BLD_MASK;
|
|
arch = (sys_id >> SYS_ID_ARCH_SHIFT) & SYS_ID_ARCH_MASK;
|
|
|
|
assert(rev == REV_FVP);
|
|
assert(arch == ARCH_MODEL);
|
|
|
|
/*
|
|
* The build field in the SYS_ID tells which variant of the GIC
|
|
* memory is implemented by the model.
|
|
*/
|
|
switch (bld) {
|
|
case BLD_GIC_VE_MMAP:
|
|
platform_config[CONFIG_GICD_ADDR] = VE_GICD_BASE;
|
|
platform_config[CONFIG_GICC_ADDR] = VE_GICC_BASE;
|
|
platform_config[CONFIG_GICH_ADDR] = VE_GICH_BASE;
|
|
platform_config[CONFIG_GICV_ADDR] = VE_GICV_BASE;
|
|
break;
|
|
case BLD_GIC_A53A57_MMAP:
|
|
platform_config[CONFIG_GICD_ADDR] = BASE_GICD_BASE;
|
|
platform_config[CONFIG_GICC_ADDR] = BASE_GICC_BASE;
|
|
platform_config[CONFIG_GICH_ADDR] = BASE_GICH_BASE;
|
|
platform_config[CONFIG_GICV_ADDR] = BASE_GICV_BASE;
|
|
break;
|
|
default:
|
|
assert(0);
|
|
}
|
|
|
|
/*
|
|
* The hbi field in the SYS_ID is 0x020 for the Base FVP & 0x010
|
|
* for the Foundation FVP.
|
|
*/
|
|
switch (hbi) {
|
|
case HBI_FOUNDATION:
|
|
platform_config[CONFIG_MAX_AFF0] = 4;
|
|
platform_config[CONFIG_MAX_AFF1] = 1;
|
|
platform_config[CONFIG_CPU_SETUP] = 0;
|
|
platform_config[CONFIG_BASE_MMAP] = 0;
|
|
platform_config[CONFIG_HAS_CCI] = 0;
|
|
break;
|
|
case HBI_FVP_BASE:
|
|
midr_pn = (read_midr() >> MIDR_PN_SHIFT) & MIDR_PN_MASK;
|
|
if ((midr_pn == MIDR_PN_A57) || (midr_pn == MIDR_PN_A53))
|
|
platform_config[CONFIG_CPU_SETUP] = 1;
|
|
else
|
|
platform_config[CONFIG_CPU_SETUP] = 0;
|
|
|
|
platform_config[CONFIG_MAX_AFF0] = 4;
|
|
platform_config[CONFIG_MAX_AFF1] = 2;
|
|
platform_config[CONFIG_BASE_MMAP] = 1;
|
|
platform_config[CONFIG_HAS_CCI] = 1;
|
|
break;
|
|
default:
|
|
assert(0);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
unsigned long plat_get_ns_image_entrypoint(void)
|
|
{
|
|
return NS_IMAGE_OFFSET;
|
|
}
|