172 lines
7.1 KiB
C
172 lines
7.1 KiB
C
/*
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* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <platform.h>
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#include <fvp_pwrc.h>
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/*******************************************************************************
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* Declarations of linker defined symbols which will help us find the layout
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* of trusted SRAM
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******************************************************************************/
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extern unsigned long __RO_START__;
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extern unsigned long __RO_END__;
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extern unsigned long __COHERENT_RAM_START__;
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extern unsigned long __COHERENT_RAM_END__;
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/*
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* The next 2 constants identify the extents of the code & RO data region.
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* These addresses are used by the MMU setup code and therefore they must be
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* page-aligned. It is the responsibility of the linker script to ensure that
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* __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses.
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*/
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#define BL31_RO_BASE (unsigned long)(&__RO_START__)
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#define BL31_RO_LIMIT (unsigned long)(&__RO_END__)
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/*
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* The next 2 constants identify the extents of the coherent memory region.
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* These addresses are used by the MMU setup code and therefore they must be
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* page-aligned. It is the responsibility of the linker script to ensure that
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* __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols
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* refer to page-aligned addresses.
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*/
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#define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
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#define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
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/*******************************************************************************
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* This data structure holds information copied by BL31 from BL2 to pass
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* control to the normal world software images.
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* TODO: Can this be moved out of device memory.
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******************************************************************************/
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static el_change_info ns_entry_info
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__attribute__ ((aligned(PLATFORM_CACHE_LINE_SIZE),
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section("tzfw_coherent_mem")));
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/* Data structure which holds the extents of the trusted SRAM for BL31 */
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static meminfo bl31_tzram_layout
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__attribute__ ((aligned(PLATFORM_CACHE_LINE_SIZE),
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section("tzfw_coherent_mem")));
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meminfo *bl31_plat_sec_mem_layout(void)
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{
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return &bl31_tzram_layout;
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}
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/*******************************************************************************
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* Return information about passing control to the non-trusted software images
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* to common code.TODO: In the initial architecture, the image after BL31 will
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* always run in the non-secure state. In the final architecture there
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* will be a series of images. This function will need enhancement then
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******************************************************************************/
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el_change_info *bl31_get_next_image_info(void)
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{
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return &ns_entry_info;
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}
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/*******************************************************************************
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* Perform any BL31 specific platform actions. Here we copy parameters passed
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* by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they are lost
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* (potentially). This is done before the MMU is initialized so that the memory
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* layout can be used while creating page tables.
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******************************************************************************/
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void bl31_early_platform_setup(meminfo *mem_layout,
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void *data)
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{
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el_change_info *image_info = (el_change_info *) data;
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/* Setup the BL31 memory layout */
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bl31_tzram_layout.total_base = mem_layout->total_base;
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bl31_tzram_layout.total_size = mem_layout->total_size;
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bl31_tzram_layout.free_base = mem_layout->free_base;
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bl31_tzram_layout.free_size = mem_layout->free_size;
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bl31_tzram_layout.attr = mem_layout->attr;
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bl31_tzram_layout.next = 0;
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/* Save information about jumping into the normal world */
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ns_entry_info.entrypoint = image_info->entrypoint;
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ns_entry_info.spsr = image_info->spsr;
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ns_entry_info.args = image_info->args;
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ns_entry_info.security_state = image_info->security_state;
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ns_entry_info.next = image_info->next;
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/* Initialize the platform config for future decision making */
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platform_config_setup();
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}
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/*******************************************************************************
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* Initialize the gic, configure the CLCD and zero out variables needed by the
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* secondaries to boot up correctly.
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******************************************************************************/
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void bl31_platform_setup()
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{
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unsigned int reg_val;
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/* Initialize the gic cpu and distributor interfaces */
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gic_setup();
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/*
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* TODO: Configure the CLCD before handing control to
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* linux. Need to see if a separate driver is needed
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* instead.
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*/
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mmio_write_32(VE_SYSREGS_BASE + V2M_SYS_CFGDATA, 0);
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mmio_write_32(VE_SYSREGS_BASE + V2M_SYS_CFGCTRL,
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(1ull << 31) | (1 << 30) | (7 << 20) | (0 << 16));
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/* Allow access to the System counter timer module */
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reg_val = (1 << CNTACR_RPCT_SHIFT) | (1 << CNTACR_RVCT_SHIFT);
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reg_val |= (1 << CNTACR_RFRQ_SHIFT) | (1 << CNTACR_RVOFF_SHIFT);
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reg_val |= (1 << CNTACR_RWVT_SHIFT) | (1 << CNTACR_RWPT_SHIFT);
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mmio_write_32(SYS_TIMCTL_BASE + CNTACR_BASE(0), reg_val);
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mmio_write_32(SYS_TIMCTL_BASE + CNTACR_BASE(1), reg_val);
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reg_val = (1 << CNTNSAR_NS_SHIFT(0)) | (1 << CNTNSAR_NS_SHIFT(1));
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mmio_write_32(SYS_TIMCTL_BASE + CNTNSAR, reg_val);
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/* Intialize the power controller */
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fvp_pwrc_setup();
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/* Topologies are best known to the platform. */
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plat_setup_topology();
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}
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/*******************************************************************************
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* Perform the very early platform specific architectural setup here. At the
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* moment this is only intializes the mmu in a quick and dirty way.
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******************************************************************************/
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void bl31_plat_arch_setup()
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{
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configure_mmu(&bl31_tzram_layout,
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BL31_RO_BASE,
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BL31_RO_LIMIT,
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BL31_COHERENT_RAM_BASE,
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BL31_COHERENT_RAM_LIMIT);
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}
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