Varun Wadekar e904448006 Tegra: bpmp: fixup TEGRA_CLK_SE values for Tegra186/Tegra194 ... This patch fixes the SE clock ID being used for Tegra186 and Tegra194 SoCs. Previous assumption, that both SoCs use the same clock ID, was incorrect. Change-Id: I1ef0da5547ff2e14151b53968cad9cc78fee63bd Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>		2020-03-11 13:37:26 -07:00
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drivers	Tegra: bpmp: fixup TEGRA_CLK_SE values for Tegra186/Tegra194	2020-03-11 13:37:26 -07:00
plat_memctrl.c	Tegra194: memctrl: lock some more MC SID security configs	2020-03-11 13:37:26 -07:00
plat_psci_handlers.c	Tegra: bpmp: fixup TEGRA_CLK_SE values for Tegra186/Tegra194	2020-03-11 13:37:26 -07:00
plat_secondary.c	Tegra194: store TZDRAM base/size to scratch registers	2020-03-11 13:31:12 -07:00
plat_setup.c	spe: Use generic console_t data structure	2020-02-25 09:34:38 +00:00
plat_sip_calls.c	Tegra194: remove support for simulated system suspend	2020-01-31 13:21:46 -08:00
plat_smmu.c	Tegra194: smmu: add PCIE0R1 mc reg to system suspend save list	2020-01-23 09:03:01 -08:00
plat_trampoline.S	Tegra194: smmu: add PCIE0R1 mc reg to system suspend save list	2020-01-23 09:03:01 -08:00
platform_t194.mk	Tegra194: enable spe-console functionality	2020-01-28 09:43:10 +00:00