43 lines
936 B
C
43 lines
936 B
C
/*
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* Copyright 2021 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#include <cci.h>
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#include <common/debug.h>
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#include <ls_interconnect.h>
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#include <mmio.h>
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#include <platform_def.h>
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void erratum_a008850_early(void)
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{
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/* part 1 of 2 */
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uintptr_t cci_base = NXP_CCI_ADDR;
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uint32_t val = mmio_read_32(cci_base + CTRL_OVERRIDE_REG);
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/* enabling forced barrier termination on CCI400 */
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mmio_write_32(cci_base + CTRL_OVERRIDE_REG,
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(val | CCI_TERMINATE_BARRIER_TX));
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}
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void erratum_a008850_post(void)
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{
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/* part 2 of 2 */
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uintptr_t cci_base = NXP_CCI_ADDR;
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uint32_t val = mmio_read_32(cci_base + CTRL_OVERRIDE_REG);
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/* Clear the BARRIER_TX bit */
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val = val & ~(CCI_TERMINATE_BARRIER_TX);
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/*
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* Disable barrier termination on CCI400, allowing
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* barriers to propagate across CCI
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*/
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mmio_write_32(cci_base + CTRL_OVERRIDE_REG, val);
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INFO("SoC workaround for Errata A008850 Post-Phase was applied\n");
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}
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