158 lines
4.4 KiB
C
158 lines
4.4 KiB
C
/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <platform_def.h>
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#include <drivers/arm/css/css_mhu_doorbell.h>
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#include <drivers/arm/css/scmi.h>
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#include <drivers/arm/css/sds.h>
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#include <common/debug.h>
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#include <lib/mmio.h>
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#include <lib/utils.h>
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#include <plat/arm/common/plat_arm.h>
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#include "n1sdp_def.h"
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/*
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* Memory information structure stored in SDS.
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* This structure holds the total DDR memory size which will be
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* used when zeroing out the entire DDR memory before enabling
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* the ECC capability in DMCs.
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*/
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struct n1sdp_mem_info {
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uint32_t ddr_size_gb;
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};
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/*
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* BL33 image information structure stored in SDS.
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* This structure holds the source & destination addresses and
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* the size of the BL33 image which will be loaded by BL31.
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*/
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struct n1sdp_bl33_info {
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uint32_t bl33_src_addr;
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uint32_t bl33_dst_addr;
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uint32_t bl33_size;
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};
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static scmi_channel_plat_info_t n1sdp_scmi_plat_info = {
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.scmi_mbx_mem = N1SDP_SCMI_PAYLOAD_BASE,
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.db_reg_addr = PLAT_CSS_MHU_BASE + CSS_SCMI_MHU_DB_REG_OFF,
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.db_preserve_mask = 0xfffffffe,
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.db_modify_mask = 0x1,
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.ring_doorbell = &mhu_ring_doorbell,
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};
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scmi_channel_plat_info_t *plat_css_get_scmi_info()
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{
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return &n1sdp_scmi_plat_info;
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}
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const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops)
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{
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return css_scmi_override_pm_ops(ops);
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}
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/*
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* N1SDP platform supports RDIMMs with ECC capability. To use the ECC
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* capability, the entire DDR memory space has to be zeroed out before
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* enabling the ECC bits in DMC620. Zeroing out several gigabytes of
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* memory from SCP is quite time consuming so the following function
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* is added to zero out the DDR memory from application processor which is
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* much faster compared to SCP. BL33 binary cannot be copied to DDR memory
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* before enabling ECC so copy_bl33 function is added to copy BL33 binary
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* from IOFPGA-DDR3 memory to main DDR4 memory.
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*/
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void dmc_ecc_setup(uint32_t ddr_size_gb)
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{
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uint64_t dram2_size;
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dram2_size = (ddr_size_gb * 1024UL * 1024UL * 1024UL) -
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ARM_DRAM1_SIZE;
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INFO("Zeroing DDR memories\n");
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zero_normalmem((void *)ARM_DRAM1_BASE, ARM_DRAM1_SIZE);
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flush_dcache_range(ARM_DRAM1_BASE, ARM_DRAM1_SIZE);
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zero_normalmem((void *)ARM_DRAM2_BASE, dram2_size);
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flush_dcache_range(ARM_DRAM2_BASE, dram2_size);
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INFO("Enabling ECC on DMCs\n");
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/* Set DMCs to CONFIG state before writing ERR0CTLR0 register */
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mmio_write_32(N1SDP_DMC0_MEMC_CMD_REG, N1SDP_DMC_MEMC_CMD_CONFIG);
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mmio_write_32(N1SDP_DMC1_MEMC_CMD_REG, N1SDP_DMC_MEMC_CMD_CONFIG);
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/* Enable ECC in DMCs */
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mmio_setbits_32(N1SDP_DMC0_ERR0CTLR0_REG, N1SDP_DMC_ERR0CTLR0_ECC_EN);
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mmio_setbits_32(N1SDP_DMC1_ERR0CTLR0_REG, N1SDP_DMC_ERR0CTLR0_ECC_EN);
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/* Set DMCs to READY state */
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mmio_write_32(N1SDP_DMC0_MEMC_CMD_REG, N1SDP_DMC_MEMC_CMD_READY);
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mmio_write_32(N1SDP_DMC1_MEMC_CMD_REG, N1SDP_DMC_MEMC_CMD_READY);
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}
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void copy_bl33(uint32_t src, uint32_t dst, uint32_t size)
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{
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uint32_t i;
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INFO("Copying BL33 to DDR memory\n");
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for (i = 0; i < size; i = i + 8)
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mmio_write_64((dst + i), mmio_read_64(src + i));
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for (i = 0; i < size; i = i + 8) {
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if (mmio_read_64(src + i) != mmio_read_64(dst + i)) {
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ERROR("Copy failed!\n");
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panic();
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}
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}
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}
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void bl31_platform_setup(void)
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{
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int ret;
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struct n1sdp_mem_info mem_info;
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struct n1sdp_bl33_info bl33_info;
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arm_bl31_platform_setup();
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ret = sds_init();
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if (ret != SDS_OK) {
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ERROR("SDS initialization failed\n");
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panic();
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}
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ret = sds_struct_read(N1SDP_SDS_MEM_INFO_STRUCT_ID,
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N1SDP_SDS_MEM_INFO_OFFSET,
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&mem_info,
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N1SDP_SDS_MEM_INFO_SIZE,
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SDS_ACCESS_MODE_NON_CACHED);
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if (ret != SDS_OK) {
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ERROR("Error getting memory info from SDS\n");
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panic();
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}
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dmc_ecc_setup(mem_info.ddr_size_gb);
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ret = sds_struct_read(N1SDP_SDS_BL33_INFO_STRUCT_ID,
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N1SDP_SDS_BL33_INFO_OFFSET,
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&bl33_info,
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N1SDP_SDS_BL33_INFO_SIZE,
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SDS_ACCESS_MODE_NON_CACHED);
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if (ret != SDS_OK) {
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ERROR("Error getting BL33 info from SDS\n");
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panic();
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}
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copy_bl33(bl33_info.bl33_src_addr,
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bl33_info.bl33_dst_addr,
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bl33_info.bl33_size);
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/*
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* Pass DDR memory size info to BL33. This method is followed as
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* currently there is no BL1/BL2 involved in boot flow of N1SDP.
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* When TBBR is implemented for N1SDP, this method should be removed
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* and DDR memory size shoule be passed to BL33 using NT_FW_CONFIG
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* passing mechanism.
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*/
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mmio_write_32(N1SDP_DDR_MEM_INFO_BASE, mem_info.ddr_size_gb);
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}
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