64 lines
1.8 KiB
C
64 lines
1.8 KiB
C
/*
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* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <arch_helpers.h>
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#include <bl_common.h>
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#include <console.h>
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#include <platform_def.h>
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#include <xlat_mmu_helpers.h>
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#include <xlat_tables_defs.h>
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#include "../../bl1/bl1_private.h"
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#include "rpi3_private.h"
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/* Data structure which holds the extents of the trusted SRAM for BL1 */
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static meminfo_t bl1_tzram_layout;
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meminfo_t *bl1_plat_sec_mem_layout(void)
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{
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return &bl1_tzram_layout;
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}
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/*******************************************************************************
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* Perform any BL1 specific platform actions.
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******************************************************************************/
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void bl1_early_platform_setup(void)
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{
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/* Initialize the console to provide early debug support */
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console_init(PLAT_RPI3_UART_BASE, PLAT_RPI3_UART_CLK_IN_HZ,
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PLAT_RPI3_UART_BAUDRATE);
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/* Allow BL1 to see the whole Trusted RAM */
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bl1_tzram_layout.total_base = BL_RAM_BASE;
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bl1_tzram_layout.total_size = BL_RAM_SIZE;
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}
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/******************************************************************************
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* Perform the very early platform specific architecture setup. This only
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* does basic initialization. Later architectural setup (bl1_arch_setup())
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* does not do anything platform specific.
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*****************************************************************************/
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void bl1_plat_arch_setup(void)
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{
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rpi3_setup_page_tables(bl1_tzram_layout.total_base,
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bl1_tzram_layout.total_size,
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BL_CODE_BASE, BL1_CODE_END,
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BL1_RO_DATA_BASE, BL1_RO_DATA_END
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#if USE_COHERENT_MEM
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, BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END
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#endif
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);
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enable_mmu_el3(0);
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}
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void bl1_platform_setup(void)
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{
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/* Initialise the IO layer and register platform IO devices */
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plat_rpi3_io_setup();
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}
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