166 lines
4.6 KiB
C
166 lines
4.6 KiB
C
/*
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* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef SE_PRIVATE_H
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#define SE_PRIVATE_H
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#include <lib/utils_def.h>
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#include <tegra_def.h>
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/* SE0 security register */
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#define SE0_SECURITY U(0x18)
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#define SE0_SECURITY_SE_SOFT_SETTING (((uint32_t)1) << 16U)
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/* SE0 SHA GSCID register */
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#define SE0_SHA_GSCID_0 U(0x100)
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/* SE0 config register */
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#define SE0_SHA_CONFIG U(0x104)
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#define SE0_SHA_TASK_CONFIG U(0x108)
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#define SE0_SHA_CONFIG_HW_INIT_HASH (((uint32_t)1) << 0U)
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#define SE0_SHA_CONFIG_HW_INIT_HASH_DISABLE U(0)
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#define SE0_CONFIG_ENC_ALG_SHIFT U(12)
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#define SE0_CONFIG_ENC_ALG_SHA \
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(((uint32_t)3) << SE0_CONFIG_ENC_ALG_SHIFT)
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#define SE0_CONFIG_DEC_ALG_SHIFT U(8)
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#define SE0_CONFIG_DEC_ALG_NOP \
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(((uint32_t)0) << SE0_CONFIG_DEC_ALG_SHIFT)
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#define SE0_CONFIG_DST_SHIFT U(2)
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#define SE0_CONFIG_DST_HASHREG \
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(((uint32_t)1) << SE0_CONFIG_DST_SHIFT)
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#define SHA256_HASH_SIZE_BYTES U(256)
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#define SE0_CONFIG_ENC_MODE_SHIFT U(24)
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#define SE0_CONFIG_ENC_MODE_SHA256 \
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(((uint32_t)5) << SE0_CONFIG_ENC_MODE_SHIFT)
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/* SHA input message length */
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#define SE0_IN_ADDR U(0x10c)
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#define SE0_IN_HI_ADDR_HI U(0x110)
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#define SE0_IN_HI_ADDR_HI_0_MSB_SHIFT U(24)
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/* SHA input message length */
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#define SE0_SHA_MSG_LENGTH_0 U(0x11c)
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#define SE0_SHA_MSG_LENGTH_1 U(0x120)
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#define SE0_SHA_MSG_LENGTH_2 U(0x124)
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#define SE0_SHA_MSG_LENGTH_3 U(0x128)
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/* SHA input message left */
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#define SE0_SHA_MSG_LEFT_0 U(0x12c)
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#define SE0_SHA_MSG_LEFT_1 U(0x130)
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#define SE0_SHA_MSG_LEFT_2 U(0x134)
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#define SE0_SHA_MSG_LEFT_3 U(0x138)
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/* SE HASH-RESULT */
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#define SE0_SHA_HASH_RESULT_0 U(0x13c)
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/* SE OPERATION */
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#define SE0_OPERATION_REG_OFFSET U(0x17c)
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#define SE0_UNIT_OPERATION_PKT_LASTBUF_SHIFT U(16)
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#define SE0_UNIT_OPERATION_PKT_LASTBUF_FIELD \
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((uint32_t)0x1 << SE0_UNIT_OPERATION_PKT_LASTBUF_SHIFT)
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#define SE0_OPERATION_SHIFT U(0)
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#define SE0_OP_START \
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(((uint32_t)0x1) << SE0_OPERATION_SHIFT)
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/* SE Interrupt */
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#define SE0_SHA_INT_ENABLE U(0x180)
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#define SE0_INT_STATUS_REG_OFFSET U(0x184)
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#define SE0_INT_OP_DONE_SHIFT U(4)
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#define SE0_INT_OP_DONE_CLEAR \
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(((uint32_t)0U) << SE0_INT_OP_DONE_SHIFT)
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#define SE0_INT_OP_DONE(x) \
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((x) & (((uint32_t)0x1U) << SE0_INT_OP_DONE_SHIFT))
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/* SE SHA Status */
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#define SE0_SHA_STATUS_0 U(0x188)
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#define SE0_SHA_STATUS_IDLE U(0)
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/* SE error status */
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#define SE0_ERR_STATUS_REG_OFFSET U(0x18c)
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#define SE0_ERR_STATUS_CLEAR U(0)
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/* SE error status */
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#define SECURE_SCRATCH_TZDRAM_SHA256_HASH_START SECURE_SCRATCH_RSV68_LO
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#define SECURE_SCRATCH_TZDRAM_SHA256_HASH_END SECURE_SCRATCH_RSV71_HI
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/* SE0_INT_ENABLE_0 */
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#define SE0_INT_ENABLE U(0x88)
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#define SE0_DISABLE_ALL_INT U(0x0)
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/* SE0_INT_STATUS_0 */
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#define SE0_INT_STATUS U(0x8C)
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#define SE0_CLEAR_ALL_INT_STATUS U(0x3F)
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/* SE0_SHA_INT_STATUS_0 */
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#define SHA_INT_STATUS U(0x184)
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#define SHA_SE_OP_DONE (U(1) << 4)
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/* SE0_SHA_ERR_STATUS_0 */
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#define SHA_ERR_STATUS U(0x18C)
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/* SE0_AES0_INT_STATUS_0 */
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#define AES0_INT_STATUS U(0x2F0)
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#define AES0_SE_OP_DONE (U(1) << 4)
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/* SE0_AES0_ERR_STATUS_0 */
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#define AES0_ERR_STATUS U(0x2F8)
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/* SE0_AES1_INT_STATUS_0 */
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#define AES1_INT_STATUS U(0x4F0)
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/* SE0_AES1_ERR_STATUS_0 */
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#define AES1_ERR_STATUS U(0x4F8)
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/* SE0_RSA_INT_STATUS_0 */
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#define RSA_INT_STATUS U(0x758)
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/* SE0_RSA_ERR_STATUS_0 */
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#define RSA_ERR_STATUS U(0x760)
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/* SE0_AES0_OPERATION_0 */
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#define AES0_OPERATION U(0x238)
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#define OP_MASK_BITS U(0x7)
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#define SE_OP_CTX_SAVE U(0x3)
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/* SE0_AES0_CTX_SAVE_CONFIG_0 */
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#define CTX_SAVE_CONFIG U(0x2D4)
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/* SE0_AES0_CTX_SAVE_AUTO_STATUS_0 */
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#define CTX_SAVE_AUTO_STATUS U(0x300)
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#define CTX_SAVE_AUTO_SE_READY U(0xFF)
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#define CTX_SAVE_AUTO_SE_BUSY (U(0x1) << 31)
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/* SE0_AES0_CTX_SAVE_AUTO_CTRL_0 */
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#define CTX_SAVE_AUTO_CTRL U(0x304)
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#define SE_CTX_SAVE_AUTO_EN (U(0x1) << 0)
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#define SE_CTX_SAVE_AUTO_LOCK_EN (U(0x1) << 1)
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/* SE0_AES0_CTX_SAVE_AUTO_START_ADDR_0 */
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#define CTX_SAVE_AUTO_START_ADDR U(0x308)
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/* SE0_AES0_CTX_SAVE_AUTO_START_ADDR_HI_0 */
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#define CTX_SAVE_AUTO_START_ADDR_HI U(0x30C)
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/*******************************************************************************
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* Inline functions definition
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******************************************************************************/
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static inline uint32_t tegra_se_read_32(uint32_t offset)
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{
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return mmio_read_32((uint32_t)(TEGRA_SE0_BASE + offset));
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}
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static inline void tegra_se_write_32(uint32_t offset, uint32_t val)
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{
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mmio_write_32((uint32_t)(TEGRA_SE0_BASE + offset), val);
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}
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#endif /* SE_PRIVATE_H */
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