96 lines
2.3 KiB
C
96 lines
2.3 KiB
C
/*
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* Copyright (C) 2018 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <drivers/marvell/cache_llc.h>
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#include <lib/mmio.h>
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#include <plat/common/platform.h>
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#define CCU_HTC_ASET (MVEBU_CCU_BASE(MVEBU_AP0) + 0x264)
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#define MVEBU_IO_AFFINITY (0xF00)
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#define MVEBU_SF_REG (MVEBU_REGS_BASE + 0x40)
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#define MVEBU_SF_EN BIT(8)
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#define MVEBU_DFX_REG(cluster_id) (MVEBU_REGS_BASE + 0x6F82A0 + \
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(cluster_id) * 0x4)
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#define MVEBU_DFX_CLK_EN_POS 0x3
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#define MVEBU_DFX_CL0_CLK_OFFS 16
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#define MVEBU_DFX_CL0_CLK_MASK (0xF << MVEBU_DFX_CL0_CLK_OFFS)
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#define MVEBU_DFX_CL1_CLK_OFFS 8
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#define MVEBU_DFX_CL1_CLK_MASK (0xF << MVEBU_DFX_CL1_CLK_OFFS)
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#ifdef MVEBU_SOC_AP807
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static void plat_enable_snoop_filter(void)
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{
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int cpu_id = plat_my_core_pos();
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/* Snoop filter needs to be enabled once per cluster */
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if (cpu_id % 2)
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return;
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mmio_setbits_32(MVEBU_SF_REG, MVEBU_SF_EN);
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}
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#endif
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#ifndef MVEBU_SOC_AP807
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static void plat_config_dfx_clock(void)
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{
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int cluster_id = plat_my_core_pos();
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uint32_t val;
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/* DFX clock needs to be configured once per cluster */
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if ((cluster_id % PLAT_MAX_CPUS_PER_CLUSTER) != 0) {
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return;
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}
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val = mmio_read_32(MVEBU_DFX_REG(cluster_id / PLAT_MAX_CPUS_PER_CLUSTER));
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if (cluster_id == 0) {
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val &= ~MVEBU_DFX_CL0_CLK_MASK;
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val |= (MVEBU_DFX_CLK_EN_POS << MVEBU_DFX_CL0_CLK_OFFS);
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} else {
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val &= ~MVEBU_DFX_CL1_CLK_MASK;
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val |= (MVEBU_DFX_CLK_EN_POS << MVEBU_DFX_CL1_CLK_OFFS);
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}
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mmio_write_32(MVEBU_DFX_REG(cluster_id / PLAT_MAX_CPUS_PER_CLUSTER), val);
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}
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#endif
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static void plat_enable_affinity(void)
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{
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int cluster_id;
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int affinity;
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/* set CPU Affinity */
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cluster_id = plat_my_core_pos() / PLAT_MARVELL_CLUSTER_CORE_COUNT;
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affinity = (MVEBU_IO_AFFINITY | (1 << cluster_id));
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mmio_write_32(CCU_HTC_ASET, affinity);
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/* set barier */
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isb();
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}
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void marvell_psci_arch_init(int die_index)
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{
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#if LLC_ENABLE
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/* check if LLC is in exclusive mode
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* as L2 is configured to UniqueClean eviction
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* (in a8k reset handler)
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*/
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if (llc_is_exclusive(0) == 0)
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ERROR("LLC should be configured to exclusice mode\n");
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#endif
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/* Enable Affinity */
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plat_enable_affinity();
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#ifdef MVEBU_SOC_AP807
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plat_enable_snoop_filter();
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#else
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plat_config_dfx_clock();
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#endif
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}
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