47 lines
1.6 KiB
C
47 lines
1.6 KiB
C
/*
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __CORTEX_A75_H__
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#define __CORTEX_A75_H__
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/* Cortex-A75 MIDR */
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#define CORTEX_A75_MIDR 0x410fd0a0
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/*******************************************************************************
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* CPU Extended Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A75_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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#define CORTEX_A75_CPUECTLR_EL1 S3_0_C15_C1_4
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/* Definitions of register field mask in CORTEX_A75_CPUPWRCTLR_EL1 */
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#define CORTEX_A75_CORE_PWRDN_EN_MASK 0x1
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#define CORTEX_A75_ACTLR_AMEN_BIT (U(1) << 4)
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/*
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* The Cortex-A75 core implements five counters, 0-4. Events 0, 1, 2, are
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* fixed and are enabled (Group 0). Events 3 and 4 (Group 1) are
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* programmable by programming the appropriate Event count bits in
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* CPUAMEVTYPER<n> register and are disabled by default. Platforms may
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* enable this with suitable programming.
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*/
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#define CORTEX_A75_AMU_NR_COUNTERS 5
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#define CORTEX_A75_AMU_GROUP0_MASK 0x7
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#define CORTEX_A75_AMU_GROUP1_MASK (0 << 3)
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#ifndef __ASSEMBLY__
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#include <stdint.h>
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uint64_t cortex_a75_amu_cnt_read(int idx);
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void cortex_a75_amu_cnt_write(int idx, uint64_t val);
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unsigned int cortex_a75_amu_read_cpuamcntenset_el0(void);
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unsigned int cortex_a75_amu_read_cpuamcntenclr_el0(void);
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void cortex_a75_amu_write_cpuamcntenset_el0(unsigned int mask);
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void cortex_a75_amu_write_cpuamcntenclr_el0(unsigned int mask);
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#endif /* __ASSEMBLY__ */
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#endif /* __CORTEX_A75_H__ */
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