6a655a85c0
Leave the caches on and explicitly flush any data that may be stale when the core is powered down. This prevents non-coherent interconnect access which has negative side- effects on AM65x. Signed-off-by: Andrew F. Davis <afd@ti.com> |
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aarch32 | ||
aarch64 | ||
cpu-ops.mk | ||
errata_report.c |