95 lines
4.1 KiB
C
95 lines
4.1 KiB
C
/*
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* Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef ARM_PAS_DEF_H
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#define ARM_PAS_DEF_H
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#include <lib/gpt_rme/gpt_rme.h>
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#include <plat/arm/common/arm_def.h>
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/*****************************************************************************
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* PAS regions used to initialize the Granule Protection Table (GPT)
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****************************************************************************/
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/*
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* The PA space is initially mapped in the GPT as follows:
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*
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* ============================================================================
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* Base Addr| Size |L? GPT|PAS |Content |Comment
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* ============================================================================
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* 0GB | 1GB |L0 GPT|ANY |TBROM (EL3 code) |Fixed mapping
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* | | | |TSRAM (EL3 data) |
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* | | | |IO (incl.UARTs & GIC) |
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* ----------------------------------------------------------------------------
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* 1GB | 1GB |L0 GPT|ANY |IO |Fixed mapping
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* ----------------------------------------------------------------------------
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* 2GB | 1GB |L1 GPT|NS |DRAM (NS Kernel) |Use T.Descrip
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* ----------------------------------------------------------------------------
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* 3GB |1GB-64MB |L1 GPT|NS |DRAM (NS Kernel) |Use T.Descrip
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* ----------------------------------------------------------------------------
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* 4GB-64MB |64MB-32MB | | | |
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* | -4MB |L1 GPT|SECURE|DRAM TZC |Use T.Descrip
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* ----------------------------------------------------------------------------
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* 4GB-32MB | | | | |
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* -3MB-1MB |32MB |L1 GPT|REALM |RMM |Use T.Descrip
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* ----------------------------------------------------------------------------
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* 4GB-3MB | | | | |
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* -1MB |3MB |L1 GPT|ROOT |EL3 DRAM data |Use T.Descrip
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* ----------------------------------------------------------------------------
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* 4GB-1MB |1MB |L1 GPT|ROOT |DRAM (L1 GPTs, SCP TZC) |Fixed mapping
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* ============================================================================
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*
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* - 4KB of L0 GPT reside in TSRAM, on top of the CONFIG section.
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* - ~1MB of L1 GPTs reside at the top of DRAM1 (TZC area).
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* - The first 1GB region has GPT_GPI_ANY and, therefore, is not protected by
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* the GPT.
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* - The DRAM TZC area is split into three regions: the L1 GPT region and
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* 3MB of region below that are defined as GPT_GPI_ROOT, 32MB Realm region
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* below that is defined as GPT_GPI_REALM and the rest of it is defined as
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* GPT_GPI_SECURE.
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*/
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/* TODO: This might not be the best way to map the PAS */
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/* Device memory 0 to 2GB */
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#define ARM_PAS_1_BASE (U(0))
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#define ARM_PAS_1_SIZE ((ULL(1)<<31)) /* 2GB */
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/* NS memory 2GB to (end - 64MB) */
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#define ARM_PAS_2_BASE (ARM_PAS_1_BASE + ARM_PAS_1_SIZE)
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#define ARM_PAS_2_SIZE (ARM_NS_DRAM1_SIZE)
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/* Secure TZC region */
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#define ARM_PAS_3_BASE (ARM_AP_TZC_DRAM1_BASE)
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#define ARM_PAS_3_SIZE (ARM_AP_TZC_DRAM1_SIZE)
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#define ARM_PAS_GPI_ANY MAP_GPT_REGION(ARM_PAS_1_BASE, \
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ARM_PAS_1_SIZE, \
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GPT_GPI_ANY)
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#define ARM_PAS_KERNEL GPT_MAP_REGION_GRANULE(ARM_PAS_2_BASE, \
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ARM_PAS_2_SIZE, \
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GPT_GPI_NS)
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#define ARM_PAS_SECURE GPT_MAP_REGION_GRANULE(ARM_PAS_3_BASE, \
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ARM_PAS_3_SIZE, \
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GPT_GPI_SECURE)
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#define ARM_PAS_REALM GPT_MAP_REGION_GRANULE(ARM_REALM_BASE, \
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ARM_REALM_SIZE, \
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GPT_GPI_REALM)
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#define ARM_PAS_EL3_DRAM GPT_MAP_REGION_GRANULE(ARM_EL3_TZC_DRAM1_BASE, \
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ARM_EL3_TZC_DRAM1_SIZE, \
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GPT_GPI_ROOT)
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#define ARM_PAS_GPTS GPT_MAP_REGION_GRANULE(ARM_L1_GPT_ADDR_BASE, \
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ARM_L1_GPT_SIZE, \
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GPT_GPI_ROOT)
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/* GPT Configuration options */
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#define PLATFORM_L0GPTSZ GPCCR_L0GPTSZ_30BITS
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#endif /* ARM_PAS_DEF_H */
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