305 lines
10 KiB
C
305 lines
10 KiB
C
/*
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* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <smmu.h>
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#include <tegra_def.h>
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#include <tegra_mc_def.h>
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#define BOARD_SYSTEM_FPGA_BASE U(1)
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#define BASE_CONFIG_SMMU_DEVICES U(2)
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#define MAX_NUM_SMMU_DEVICES U(3)
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static uint32_t tegra_misc_read_32(uint32_t off)
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{
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return mmio_read_32((uintptr_t)TEGRA_MISC_BASE + off);
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}
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/*******************************************************************************
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* Array to hold SMMU context for Tegra194
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******************************************************************************/
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static __attribute__((aligned(16))) smmu_regs_t tegra194_smmu_context[] = {
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_START_OF_TABLE_,
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mc_make_sid_security_cfg(HDAR),
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mc_make_sid_security_cfg(HOST1XDMAR),
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mc_make_sid_security_cfg(NVENCSRD),
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mc_make_sid_security_cfg(SATAR),
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mc_make_sid_security_cfg(NVENCSWR),
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mc_make_sid_security_cfg(HDAW),
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mc_make_sid_security_cfg(SATAW),
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mc_make_sid_security_cfg(ISPRA),
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mc_make_sid_security_cfg(ISPFALR),
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mc_make_sid_security_cfg(ISPWA),
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mc_make_sid_security_cfg(ISPWB),
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mc_make_sid_security_cfg(XUSB_HOSTR),
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mc_make_sid_security_cfg(XUSB_HOSTW),
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mc_make_sid_security_cfg(XUSB_DEVR),
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mc_make_sid_security_cfg(XUSB_DEVW),
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mc_make_sid_security_cfg(TSECSRD),
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mc_make_sid_security_cfg(TSECSWR),
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mc_make_sid_security_cfg(SDMMCRA),
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mc_make_sid_security_cfg(SDMMCR),
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mc_make_sid_security_cfg(SDMMCRAB),
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mc_make_sid_security_cfg(SDMMCWA),
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mc_make_sid_security_cfg(SDMMCW),
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mc_make_sid_security_cfg(SDMMCWAB),
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mc_make_sid_security_cfg(VICSRD),
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mc_make_sid_security_cfg(VICSWR),
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mc_make_sid_security_cfg(VIW),
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mc_make_sid_security_cfg(NVDECSRD),
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mc_make_sid_security_cfg(NVDECSWR),
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mc_make_sid_security_cfg(APER),
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mc_make_sid_security_cfg(APEW),
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mc_make_sid_security_cfg(NVJPGSRD),
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mc_make_sid_security_cfg(NVJPGSWR),
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mc_make_sid_security_cfg(SESRD),
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mc_make_sid_security_cfg(SESWR),
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mc_make_sid_security_cfg(AXIAPR),
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mc_make_sid_security_cfg(AXIAPW),
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mc_make_sid_security_cfg(ETRR),
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mc_make_sid_security_cfg(ETRW),
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mc_make_sid_security_cfg(TSECSRDB),
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mc_make_sid_security_cfg(TSECSWRB),
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mc_make_sid_security_cfg(AXISR),
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mc_make_sid_security_cfg(AXISW),
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mc_make_sid_security_cfg(EQOSR),
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mc_make_sid_security_cfg(EQOSW),
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mc_make_sid_security_cfg(UFSHCR),
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mc_make_sid_security_cfg(UFSHCW),
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mc_make_sid_security_cfg(NVDISPLAYR),
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mc_make_sid_security_cfg(BPMPR),
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mc_make_sid_security_cfg(BPMPW),
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mc_make_sid_security_cfg(BPMPDMAR),
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mc_make_sid_security_cfg(BPMPDMAW),
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mc_make_sid_security_cfg(AONR),
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mc_make_sid_security_cfg(AONW),
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mc_make_sid_security_cfg(AONDMAR),
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mc_make_sid_security_cfg(AONDMAW),
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mc_make_sid_security_cfg(SCER),
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mc_make_sid_security_cfg(SCEW),
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mc_make_sid_security_cfg(SCEDMAR),
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mc_make_sid_security_cfg(SCEDMAW),
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mc_make_sid_security_cfg(APEDMAR),
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mc_make_sid_security_cfg(APEDMAW),
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mc_make_sid_security_cfg(NVDISPLAYR1),
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mc_make_sid_security_cfg(VICSRD1),
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mc_make_sid_security_cfg(NVDECSRD1),
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mc_make_sid_security_cfg(VIFALR),
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mc_make_sid_security_cfg(VIFALW),
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mc_make_sid_security_cfg(DLA0RDA),
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mc_make_sid_security_cfg(DLA0FALRDB),
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mc_make_sid_security_cfg(DLA0WRA),
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mc_make_sid_security_cfg(DLA0FALWRB),
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mc_make_sid_security_cfg(DLA1RDA),
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mc_make_sid_security_cfg(DLA1FALRDB),
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mc_make_sid_security_cfg(DLA1WRA),
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mc_make_sid_security_cfg(DLA1FALWRB),
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mc_make_sid_security_cfg(PVA0RDA),
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mc_make_sid_security_cfg(PVA0RDB),
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mc_make_sid_security_cfg(PVA0RDC),
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mc_make_sid_security_cfg(PVA0WRA),
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mc_make_sid_security_cfg(PVA0WRB),
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mc_make_sid_security_cfg(PVA0WRC),
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mc_make_sid_security_cfg(PVA1RDA),
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mc_make_sid_security_cfg(PVA1RDB),
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mc_make_sid_security_cfg(PVA1RDC),
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mc_make_sid_security_cfg(PVA1WRA),
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mc_make_sid_security_cfg(PVA1WRB),
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mc_make_sid_security_cfg(PVA1WRC),
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mc_make_sid_security_cfg(RCER),
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mc_make_sid_security_cfg(RCEW),
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mc_make_sid_security_cfg(RCEDMAR),
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mc_make_sid_security_cfg(RCEDMAW),
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mc_make_sid_security_cfg(NVENC1SRD),
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mc_make_sid_security_cfg(NVENC1SWR),
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mc_make_sid_security_cfg(PCIE0R),
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mc_make_sid_security_cfg(PCIE0W),
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mc_make_sid_security_cfg(PCIE1R),
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mc_make_sid_security_cfg(PCIE1W),
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mc_make_sid_security_cfg(PCIE2AR),
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mc_make_sid_security_cfg(PCIE2AW),
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mc_make_sid_security_cfg(PCIE3R),
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mc_make_sid_security_cfg(PCIE3W),
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mc_make_sid_security_cfg(PCIE4R),
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mc_make_sid_security_cfg(PCIE4W),
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mc_make_sid_security_cfg(PCIE5R),
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mc_make_sid_security_cfg(PCIE5W),
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mc_make_sid_security_cfg(ISPFALW),
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mc_make_sid_security_cfg(DLA0RDA1),
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mc_make_sid_security_cfg(DLA1RDA1),
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mc_make_sid_security_cfg(PVA0RDA1),
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mc_make_sid_security_cfg(PVA0RDB1),
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mc_make_sid_security_cfg(PVA1RDA1),
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mc_make_sid_security_cfg(PVA1RDB1),
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mc_make_sid_security_cfg(PCIE5R1),
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mc_make_sid_security_cfg(NVENCSRD1),
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mc_make_sid_security_cfg(NVENC1SRD1),
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mc_make_sid_security_cfg(ISPRA1),
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mc_make_sid_security_cfg(MIU0R),
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mc_make_sid_security_cfg(MIU0W),
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mc_make_sid_security_cfg(MIU1R),
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mc_make_sid_security_cfg(MIU1W),
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mc_make_sid_security_cfg(MIU2R),
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mc_make_sid_security_cfg(MIU2W),
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mc_make_sid_security_cfg(MIU3R),
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mc_make_sid_security_cfg(MIU3W),
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mc_make_sid_override_cfg(HDAR),
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mc_make_sid_override_cfg(HOST1XDMAR),
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mc_make_sid_override_cfg(NVENCSRD),
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mc_make_sid_override_cfg(SATAR),
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mc_make_sid_override_cfg(NVENCSWR),
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mc_make_sid_override_cfg(HDAW),
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mc_make_sid_override_cfg(SATAW),
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mc_make_sid_override_cfg(ISPRA),
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mc_make_sid_override_cfg(ISPFALR),
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mc_make_sid_override_cfg(ISPWA),
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mc_make_sid_override_cfg(ISPWB),
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mc_make_sid_override_cfg(XUSB_HOSTR),
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mc_make_sid_override_cfg(XUSB_HOSTW),
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mc_make_sid_override_cfg(XUSB_DEVR),
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mc_make_sid_override_cfg(XUSB_DEVW),
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mc_make_sid_override_cfg(TSECSRD),
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mc_make_sid_override_cfg(TSECSWR),
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mc_make_sid_override_cfg(SDMMCRA),
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mc_make_sid_override_cfg(SDMMCR),
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mc_make_sid_override_cfg(SDMMCRAB),
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mc_make_sid_override_cfg(SDMMCWA),
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mc_make_sid_override_cfg(SDMMCW),
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mc_make_sid_override_cfg(SDMMCWAB),
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mc_make_sid_override_cfg(VICSRD),
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mc_make_sid_override_cfg(VICSWR),
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mc_make_sid_override_cfg(VIW),
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mc_make_sid_override_cfg(NVDECSRD),
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mc_make_sid_override_cfg(NVDECSWR),
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mc_make_sid_override_cfg(APER),
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mc_make_sid_override_cfg(APEW),
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mc_make_sid_override_cfg(NVJPGSRD),
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mc_make_sid_override_cfg(NVJPGSWR),
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mc_make_sid_override_cfg(SESRD),
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mc_make_sid_override_cfg(SESWR),
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mc_make_sid_override_cfg(AXIAPR),
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mc_make_sid_override_cfg(AXIAPW),
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mc_make_sid_override_cfg(ETRR),
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mc_make_sid_override_cfg(ETRW),
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mc_make_sid_override_cfg(TSECSRDB),
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mc_make_sid_override_cfg(TSECSWRB),
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mc_make_sid_override_cfg(AXISR),
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mc_make_sid_override_cfg(AXISW),
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mc_make_sid_override_cfg(EQOSR),
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mc_make_sid_override_cfg(EQOSW),
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mc_make_sid_override_cfg(UFSHCR),
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mc_make_sid_override_cfg(UFSHCW),
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mc_make_sid_override_cfg(NVDISPLAYR),
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mc_make_sid_override_cfg(BPMPR),
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mc_make_sid_override_cfg(BPMPW),
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mc_make_sid_override_cfg(BPMPDMAR),
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mc_make_sid_override_cfg(BPMPDMAW),
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mc_make_sid_override_cfg(AONR),
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mc_make_sid_override_cfg(AONW),
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mc_make_sid_override_cfg(AONDMAR),
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mc_make_sid_override_cfg(AONDMAW),
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mc_make_sid_override_cfg(SCER),
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mc_make_sid_override_cfg(SCEW),
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mc_make_sid_override_cfg(SCEDMAR),
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mc_make_sid_override_cfg(SCEDMAW),
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mc_make_sid_override_cfg(APEDMAR),
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mc_make_sid_override_cfg(APEDMAW),
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mc_make_sid_override_cfg(NVDISPLAYR1),
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mc_make_sid_override_cfg(VICSRD1),
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mc_make_sid_override_cfg(NVDECSRD1),
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mc_make_sid_override_cfg(VIFALR),
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mc_make_sid_override_cfg(VIFALW),
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mc_make_sid_override_cfg(DLA0RDA),
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mc_make_sid_override_cfg(DLA0FALRDB),
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mc_make_sid_override_cfg(DLA0WRA),
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mc_make_sid_override_cfg(DLA0FALWRB),
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mc_make_sid_override_cfg(DLA1RDA),
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mc_make_sid_override_cfg(DLA1FALRDB),
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mc_make_sid_override_cfg(DLA1WRA),
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mc_make_sid_override_cfg(DLA1FALWRB),
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mc_make_sid_override_cfg(PVA0RDA),
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mc_make_sid_override_cfg(PVA0RDB),
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mc_make_sid_override_cfg(PVA0RDC),
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mc_make_sid_override_cfg(PVA0WRA),
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mc_make_sid_override_cfg(PVA0WRB),
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mc_make_sid_override_cfg(PVA0WRC),
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mc_make_sid_override_cfg(PVA1RDA),
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mc_make_sid_override_cfg(PVA1RDB),
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mc_make_sid_override_cfg(PVA1RDC),
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mc_make_sid_override_cfg(PVA1WRA),
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mc_make_sid_override_cfg(PVA1WRB),
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mc_make_sid_override_cfg(PVA1WRC),
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mc_make_sid_override_cfg(RCER),
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mc_make_sid_override_cfg(RCEW),
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mc_make_sid_override_cfg(RCEDMAR),
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mc_make_sid_override_cfg(RCEDMAW),
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mc_make_sid_override_cfg(NVENC1SRD),
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mc_make_sid_override_cfg(NVENC1SWR),
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mc_make_sid_override_cfg(PCIE0R),
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mc_make_sid_override_cfg(PCIE0W),
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mc_make_sid_override_cfg(PCIE1R),
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mc_make_sid_override_cfg(PCIE1W),
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mc_make_sid_override_cfg(PCIE2AR),
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mc_make_sid_override_cfg(PCIE2AW),
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mc_make_sid_override_cfg(PCIE3R),
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mc_make_sid_override_cfg(PCIE3W),
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mc_make_sid_override_cfg(PCIE4R),
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mc_make_sid_override_cfg(PCIE4W),
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mc_make_sid_override_cfg(PCIE5R),
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mc_make_sid_override_cfg(PCIE5W),
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mc_make_sid_override_cfg(ISPFALW),
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mc_make_sid_override_cfg(DLA0RDA1),
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mc_make_sid_override_cfg(DLA1RDA1),
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mc_make_sid_override_cfg(PVA0RDA1),
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mc_make_sid_override_cfg(PVA0RDB1),
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mc_make_sid_override_cfg(PVA1RDA1),
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mc_make_sid_override_cfg(PVA1RDB1),
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mc_make_sid_override_cfg(PCIE5R1),
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mc_make_sid_override_cfg(NVENCSRD1),
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mc_make_sid_override_cfg(NVENC1SRD1),
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mc_make_sid_override_cfg(ISPRA1),
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mc_make_sid_override_cfg(MIU0R),
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mc_make_sid_override_cfg(MIU0W),
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mc_make_sid_override_cfg(MIU1R),
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mc_make_sid_override_cfg(MIU1W),
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mc_make_sid_override_cfg(MIU2R),
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mc_make_sid_override_cfg(MIU2W),
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mc_make_sid_override_cfg(MIU3R),
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mc_make_sid_override_cfg(MIU3W),
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smmu_make_cfg(TEGRA_SMMU0_BASE),
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smmu_make_cfg(TEGRA_SMMU2_BASE),
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smmu_bypass_cfg, /* TBU settings */
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_END_OF_TABLE_,
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};
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/*******************************************************************************
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* Handler to return the pointer to the SMMU's context struct
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******************************************************************************/
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smmu_regs_t *plat_get_smmu_ctx(void)
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{
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/* index of _END_OF_TABLE_ */
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tegra194_smmu_context[0].val = (uint32_t)ARRAY_SIZE(tegra194_smmu_context) - 1U;
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return tegra194_smmu_context;
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}
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/*******************************************************************************
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* Handler to return the support SMMU devices number
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******************************************************************************/
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uint32_t plat_get_num_smmu_devices(void)
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{
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uint32_t ret_num = MAX_NUM_SMMU_DEVICES;
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uint32_t board_revid = ((tegra_misc_read_32(MISCREG_EMU_REVID) >> \
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BOARD_SHIFT_BITS) & BOARD_MASK_BITS);
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if (board_revid == BOARD_SYSTEM_FPGA_BASE) {
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ret_num = BASE_CONFIG_SMMU_DEVICES;
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}
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return ret_num;
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}
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