208 lines
7.6 KiB
C
208 lines
7.6 KiB
C
/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch.h>
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#include <arch_helpers.h>
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#include <assert.h>
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#include <bl_common.h>
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#include <context.h>
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#include <context_mgmt.h>
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#include <debug.h>
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#include <platform.h>
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#include <platform_def.h>
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#include <platform_sp_min.h>
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#include <psci.h>
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#include <runtime_svc.h>
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#include <smcc_helpers.h>
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#include <stddef.h>
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#include <stdint.h>
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#include <string.h>
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#include <types.h>
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#include "sp_min_private.h"
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/* Pointers to per-core cpu contexts */
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static void *sp_min_cpu_ctx_ptr[PLATFORM_CORE_COUNT];
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/* SP_MIN only stores the non secure smc context */
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static smc_ctx_t sp_min_smc_context[PLATFORM_CORE_COUNT];
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/******************************************************************************
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* Define the smcc helper library API's
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*****************************************************************************/
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void *smc_get_ctx(int security_state)
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{
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assert(security_state == NON_SECURE);
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return &sp_min_smc_context[plat_my_core_pos()];
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}
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void smc_set_next_ctx(int security_state)
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{
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assert(security_state == NON_SECURE);
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/* SP_MIN stores only non secure smc context. Nothing to do here */
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}
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void *smc_get_next_ctx(void)
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{
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return &sp_min_smc_context[plat_my_core_pos()];
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}
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/*******************************************************************************
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* This function returns a pointer to the most recent 'cpu_context' structure
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* for the calling CPU that was set as the context for the specified security
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* state. NULL is returned if no such structure has been specified.
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******************************************************************************/
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void *cm_get_context(uint32_t security_state)
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{
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assert(security_state == NON_SECURE);
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return sp_min_cpu_ctx_ptr[plat_my_core_pos()];
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}
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/*******************************************************************************
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* This function sets the pointer to the current 'cpu_context' structure for the
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* specified security state for the calling CPU
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******************************************************************************/
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void cm_set_context(void *context, uint32_t security_state)
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{
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assert(security_state == NON_SECURE);
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sp_min_cpu_ctx_ptr[plat_my_core_pos()] = context;
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}
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/*******************************************************************************
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* This function returns a pointer to the most recent 'cpu_context' structure
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* for the CPU identified by `cpu_idx` that was set as the context for the
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* specified security state. NULL is returned if no such structure has been
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* specified.
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******************************************************************************/
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void *cm_get_context_by_index(unsigned int cpu_idx,
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unsigned int security_state)
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{
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assert(security_state == NON_SECURE);
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return sp_min_cpu_ctx_ptr[cpu_idx];
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}
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/*******************************************************************************
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* This function sets the pointer to the current 'cpu_context' structure for the
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* specified security state for the CPU identified by CPU index.
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******************************************************************************/
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void cm_set_context_by_index(unsigned int cpu_idx, void *context,
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unsigned int security_state)
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{
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assert(security_state == NON_SECURE);
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sp_min_cpu_ctx_ptr[cpu_idx] = context;
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}
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static void copy_cpu_ctx_to_smc_stx(const regs_t *cpu_reg_ctx,
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smc_ctx_t *next_smc_ctx)
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{
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next_smc_ctx->r0 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R0);
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next_smc_ctx->lr_mon = read_ctx_reg(cpu_reg_ctx, CTX_LR);
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next_smc_ctx->spsr_mon = read_ctx_reg(cpu_reg_ctx, CTX_SPSR);
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}
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/*******************************************************************************
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* This function invokes the PSCI library interface to initialize the
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* non secure cpu context and copies the relevant cpu context register values
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* to smc context. These registers will get programmed during `smc_exit`.
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******************************************************************************/
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static void sp_min_prepare_next_image_entry(void)
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{
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entry_point_info_t *next_image_info;
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/* Program system registers to proceed to non-secure */
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next_image_info = sp_min_plat_get_bl33_ep_info();
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assert(next_image_info);
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assert(NON_SECURE == GET_SECURITY_STATE(next_image_info->h.attr));
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INFO("SP_MIN: Preparing exit to normal world\n");
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psci_prepare_next_non_secure_ctx(next_image_info);
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smc_set_next_ctx(NON_SECURE);
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/* Copy r0, lr and spsr from cpu context to SMC context */
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copy_cpu_ctx_to_smc_stx(get_regs_ctx(cm_get_context(NON_SECURE)),
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smc_get_next_ctx());
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}
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/******************************************************************************
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* The SP_MIN main function. Do the platform and PSCI Library setup. Also
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* initialize the runtime service framework.
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*****************************************************************************/
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void sp_min_main(void)
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{
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/* Setup the arguments for PSCI Library */
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DEFINE_STATIC_PSCI_LIB_ARGS_V1(psci_args, sp_min_warm_entrypoint);
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NOTICE("SP_MIN: %s\n", version_string);
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NOTICE("SP_MIN: %s\n", build_message);
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/* Perform the SP_MIN platform setup */
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sp_min_platform_setup();
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/*
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* Initialize the PSCI library and perform the remaining generic
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* architectural setup from PSCI.
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*/
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psci_setup(&psci_args);
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/*
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* Initialize the runtime services e.g. psci
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* This is where the monitor mode will be initialized
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*/
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INFO("SP_MIN: Initializing runtime services\n");
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runtime_svc_init();
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/*
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* We are ready to enter the next EL. Prepare entry into the image
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* corresponding to the desired security state after the next ERET.
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*/
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sp_min_prepare_next_image_entry();
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}
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/******************************************************************************
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* This function is invoked during warm boot. Invoke the PSCI library
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* warm boot entry point which takes care of Architectural and platform setup/
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* restore. Copy the relevant cpu_context register values to smc context which
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* will get programmed during `smc_exit`.
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*****************************************************************************/
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void sp_min_warm_boot(void)
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{
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smc_ctx_t *next_smc_ctx;
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psci_warmboot_entrypoint();
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smc_set_next_ctx(NON_SECURE);
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next_smc_ctx = smc_get_next_ctx();
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memset(next_smc_ctx, 0, sizeof(smc_ctx_t));
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copy_cpu_ctx_to_smc_stx(get_regs_ctx(cm_get_context(NON_SECURE)),
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next_smc_ctx);
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}
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