johpow01 0e0521bdfc Workaround for Neoverse N1 erratum 1800710 ... Neoverse N1 erratum 1800710 is a Cat B erratum, present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the ECTLR_EL1 system register, which disables allocation of splintered pages in the L2 TLB. This errata is explained in this SDEN: https://static.docs.arm.com/sden885747/f/Arm_Neoverse_N1_MP050_Software_Developer_Errata_Notice_v21.pdf Signed-off-by: John Powell <john.powell@arm.com> Change-Id: Ie5b15c8bc3235e474a06a57c3ec70684361857a6		2020-06-25 19:58:35 +00:00
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aarch32	Replace __ASSEMBLY__ with compiler-builtin __ASSEMBLER__	2019-08-01 13:14:12 -07:00
aarch64	Workaround for Neoverse N1 erratum 1800710	2020-06-25 19:58:35 +00:00
errata_report.h	Replace __ASSEMBLY__ with compiler-builtin __ASSEMBLER__	2019-08-01 13:14:12 -07:00
wa_cve_2017_5715.h	Fix MISRA defects in workaround and errata framework	2018-10-29 14:41:48 +00:00
wa_cve_2018_3639.h	Fix MISRA defects in workaround and errata framework	2018-10-29 14:41:48 +00:00